Jason a718e00475 test(fpga): C-3 — align DDC ADC format test with exact conversion

2026-05-09 14:07:54 +05:45

..

9_1_Microcontroller

feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy

2026-05-07 13:29:48 +05:45

9_2_FPGA

test(fpga): C-3 — align DDC ADC format test with exact conversion

2026-05-09 14:07:54 +05:45

9_3_GUI

feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback

2026-05-07 15:20:09 +05:45

tests/cross_layer

chore(tests): retire v1 cross-layer iverilog cosim tier

2026-05-04 21:06:34 +05:45

tools

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45