9d1eb4b11c
FPGA — RX chain
matched_filter_multi_segment.v: drop the gratuitous /4 scaling on
DDC sign-extended input (was ddc_i[17:2] + ddc_i[1]); use
ddc_i[15:0] directly. fft_engine has INTERNAL_W=32 with
saturating 16-bit output, so full 16-bit input is safe. Restores
~12 dB of MF input dynamic range.
radar_receiver_final.v: remove latency_buffer (count-N-pulses-then-
prime FIFO that left frame 1 with all-zero ref). Replaced with
a single-FF alignment register on ref_i/ref_q that matches the
1-FF stage multi_segment ST_PROCESSING uses on adc_data.
Verified by tb/tb_rxb_fullchain_latency.v — autocorrelation peak
at bin 0 with peak/mean ~88x.
doppler_processor.v / mti_canceller.v / cfar_ca.v /
range_bin_decimator.v / radar_receiver_final.v / radar_system_top.v
/ usb_data_interface_ft2232h.v: switch port and parameter widths
from RP_NUM_RANGE_BINS / RP_RANGE_BIN_BITS (always 512 / 9-bit)
to RP_MAX_OUTPUT_BINS / RP_RANGE_BIN_WIDTH_MAX (auto-scales:
50T 512 / 9-bit, 200T 4096 / 12-bit). Unblocks 200T 20 km mode
at the RX module boundary; USB wire-protocol extension still
pending.
radar_receiver_final.v: doppler_frame_done_prev reset value 0 -> 1
to prevent false done pulse on cycle 1 when level signal is
HIGH at reset.
matched_filter_processing_chain.v: delete the broken `ifdef
SIMULATION inline behavioural FFT (482 lines removed). It
produced wrong-bin peaks and 100-1000x weak magnitudes. Chain
now uses production fft_engine.v + frequency_matched_filter.v
in both iverilog and Vivado. Iverilog tests are ~38x slower per
chain pass but produce correct results. Misleading "OK with
Xilinx IP" comments at three test sites updated since the FFT
is in-house, not an IP placeholder.
FPGA — testbenches
tb/tb_rxb_latency_measure.v (new): measures chain internal pipeline
depth (~2057 cycles, chirp-agnostic).
tb/tb_rxb_fullchain_latency.v (new): full-chain autocorrelation
verification — drives ddc with the same chirp samples the loader
serves as ref, finds peak position and peak/mean.
tb/tb_matched_filter_processing_chain.v: wait timeouts bumped
50000 -> 500000 cycles to accommodate production FFT pipeline.
MCU
main.cpp checkSystemHealthStatus: latch system_emergency_state on
the error_count > 10 path so the SAFE-MODE blink loop in main()
actually engages (was bypassed because predicate was false).
main.cpp: move FPGA reset BEFORE the if(PowerAmplifier) block so
adar_tr_x is driven LOW (RX commanded externally) before PA Vdd
reaches 22 V. Old reset block at the original location removed.
main.cpp MX_GPIO_Init: add GPIO_PIN_12 (FPGA reset) to the
explicit WritePin(LOW) list so the safe initial state is no
longer implicit.
main.cpp checkSystemHealth: rate-limit ADAR1000
verifyDeviceCommunication (HAL_Delay 1ms x 4 devices = 4 ms
blocking SPI burst per main-loop iteration) from every-loop to
every 2 s. readTemperature stays per-loop so over-temp
detection latency is unchanged.
USBHandler.cpp processSettingsData: dispatch threshold bumped
74 -> 82 (matches parser minimum); buffer drained after parse
attempt (slide remaining bytes left) so a false END find no
longer sticks the buffer until 256-byte overflow.
GUI
radar_protocol.py: NUM_RANGE_BINS 64 -> 512 (matches FPGA
RP_NUM_RANGE_BINS); NUM_CELLS 2048 -> 16384.
radar_protocol.py _ingest_sample: honor FPGA frame_start bit for
resync after a USB drop; capture range_profile[rbin] once per
range bin at dbin == 0 (FPGA emits the same range_i/range_q for
all 32 Doppler cells of a given range bin; previous accumulator
inflated the profile 32x).
v7/models.py RadarSettings: range_resolution 24 -> 6 m (matches
c/(2*100MHz)*4); max_distance and coverage_radius 1536 -> 3072 m;
map_size 2000 -> 4000.
v7/models.py WaveformConfig: n_range_bins 64 -> 512, fft_size
1024 -> 2048, decimation_factor 16 -> 4.
GUI_V65_Tk.py: _RANGE_PER_BIN math and stale "~24 m / ~1536 m"
comments updated.
test_v7.py: assertion values updated to match new defaults.
Tests
test_ddc_cosim_fuzz.py: remove unused os/tempfile imports, wrap
three long lines for ruff E501 compliance.
553 lines
22 KiB
Verilog
553 lines
22 KiB
Verilog
`timescale 1ns / 1ps
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// ============================================================================
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// doppler_processor.v — Staggered-PRF Doppler Processor (CORRECTED)
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// ============================================================================
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//
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// ARCHITECTURE:
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// This module implements dual 16-point FFTs for the AERIS-10 staggered-PRF
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// waveform. The radar transmits 16 long-PRI chirps followed by 16 short-PRI
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// chirps per frame (32 total). Rather than a single 32-point FFT over the
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// non-uniformly sampled frame (which is signal-processing invalid), this
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// module processes each sub-frame independently:
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//
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// Sub-frame 0 (long PRI): chirps 0..15 → 16-pt windowed FFT
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// Sub-frame 1 (short PRI): chirps 16..31 → 16-pt windowed FFT
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//
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// Each sub-frame produces 16 Doppler bins per range bin. The outputs are
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// tagged with a sub_frame bit and the 4-bit bin index is packed into the
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// existing 5-bit doppler_bin port as {sub_frame, bin[3:0]}.
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//
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// This architecture enables downstream staggered-PRF ambiguity resolution:
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// the same target velocity maps to DIFFERENT Doppler bins at different PRIs,
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// and comparing the two sub-frame results resolves velocity ambiguity.
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//
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// INTERFACE COMPATIBILITY:
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// The port list is a superset of the original module. Existing instantiations
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// that don't connect `sub_frame` will still work. The FORMAL ports are
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// retained. CHIRPS_PER_FRAME must be 32 (16 per sub-frame).
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//
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// WINDOW:
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// 16-point Hamming window (Q15), symmetric. Computed as:
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// w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
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// ============================================================================
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`include "radar_params.vh"
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// ----------------------------------------------------------------------------
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// [RX-D FIX] RANGE_BINS and range_bin port now scale with `RP_MAX_OUTPUT_BINS
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// and `RP_RANGE_BIN_WIDTH_MAX (auto-conditional on SUPPORT_LONG_RANGE).
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// 50T (no SUPPORT_LONG_RANGE): 512 bins / 9-bit — 3 km only
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// 200T (SUPPORT_LONG_RANGE): 4096 bins / 12-bit — 3 km and 20 km
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// In 3 km mode the upstream produces 512 bins (uses bins 0..511 only on 200T).
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// In 20 km mode the upstream produces 4096 bins, which the BRAMs and counters
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// can now represent without aliasing.
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// ----------------------------------------------------------------------------
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module doppler_processor_optimized #(
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parameter DOPPLER_FFT_SIZE = `RP_DOPPLER_FFT_SIZE, // 16
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parameter RANGE_BINS = `RP_MAX_OUTPUT_BINS, // 512 (50T) / 4096 (200T)
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parameter CHIRPS_PER_FRAME = `RP_CHIRPS_PER_FRAME, // 32
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parameter CHIRPS_PER_SUBFRAME = `RP_CHIRPS_PER_SUBFRAME, // 16
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parameter WINDOW_TYPE = 0, // 0=Hamming, 1=Rectangular
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parameter DATA_WIDTH = `RP_DATA_WIDTH // 16
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)(
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input wire clk,
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input wire reset_n,
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input wire [31:0] range_data,
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input wire data_valid,
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input wire new_chirp_frame,
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output reg [31:0] doppler_output,
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output reg doppler_valid,
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output reg [4:0] doppler_bin, // {sub_frame, bin[3:0]}
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output reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin, // 9-bit (50T) / 12-bit (200T)
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output reg sub_frame, // 0=long PRI, 1=short PRI
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output wire processing_active,
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output wire frame_complete,
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output reg [3:0] status
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`ifdef FORMAL
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,
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output wire [2:0] fv_state,
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output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_write_addr,
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output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_read_addr,
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output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] fv_write_range_bin,
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output wire [4:0] fv_write_chirp_index,
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output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] fv_read_range_bin,
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output wire [4:0] fv_read_doppler_index,
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output wire [9:0] fv_processing_timeout,
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output wire fv_frame_buffer_full,
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output wire fv_mem_we,
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output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_waddr_r
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`endif
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);
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// ==============================================
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// Window Coefficients — 16-point Hamming (Q15)
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// ==============================================
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// w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
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// Symmetric: w[n] = w[15-n]
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reg [DATA_WIDTH-1:0] window_coeff [0:15];
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integer w;
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initial begin
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if (WINDOW_TYPE == 0) begin
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// 16-point Hamming window, Q15 format
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// Computed: round(32767 * (0.54 - 0.46*cos(2*pi*n/15)))
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window_coeff[0] = 16'h0A3D; // 0.0800 * 32767 = 2621
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window_coeff[1] = 16'h0E5C; // 0.1116 * 32767 = 3676
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window_coeff[2] = 16'h1B6D; // 0.2138 * 32767 = 7021
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window_coeff[3] = 16'h3088; // 0.3790 * 32767 = 12424
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window_coeff[4] = 16'h4B33; // 0.5868 * 32767 = 19251
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window_coeff[5] = 16'h6573; // 0.7930 * 32767 = 25971
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window_coeff[6] = 16'h7642; // 0.9245 * 32767 = 30274
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window_coeff[7] = 16'h7F62; // 0.9932 * 32767 = 32610
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window_coeff[8] = 16'h7F62; // symmetric
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window_coeff[9] = 16'h7642;
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window_coeff[10] = 16'h6573;
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window_coeff[11] = 16'h4B33;
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window_coeff[12] = 16'h3088;
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window_coeff[13] = 16'h1B6D;
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window_coeff[14] = 16'h0E5C;
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window_coeff[15] = 16'h0A3D;
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end else begin
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for (w = 0; w < 16; w = w + 1) begin
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window_coeff[w] = 16'h7FFF;
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end
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end
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end
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// ==============================================
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// Memory Declaration - FIXED SIZE
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// ==============================================
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localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] doppler_i_mem [0:MEM_DEPTH-1];
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] doppler_q_mem [0:MEM_DEPTH-1];
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// ==============================================
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// Control Registers
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// ==============================================
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reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] write_range_bin;
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reg [4:0] write_chirp_index;
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reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] read_range_bin;
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reg [4:0] read_doppler_index;
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reg frame_buffer_full;
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reg [9:0] chirps_received;
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reg [1:0] chirp_state;
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// Sub-frame tracking
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reg current_sub_frame; // 0=processing long, 1=processing short
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// ==============================================
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// FFT Interface
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// ==============================================
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reg fft_start;
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wire fft_ready;
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reg [DATA_WIDTH-1:0] fft_input_i;
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reg [DATA_WIDTH-1:0] fft_input_q;
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reg signed [31:0] mult_i, mult_q;
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reg signed [DATA_WIDTH-1:0] window_val_reg;
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reg signed [31:0] mult_i_raw, mult_q_raw;
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reg fft_input_valid;
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reg fft_input_last;
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wire [DATA_WIDTH-1:0] fft_output_i;
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wire [DATA_WIDTH-1:0] fft_output_q;
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wire fft_output_valid;
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wire fft_output_last;
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// ==============================================
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// Addressing
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// ==============================================
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wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_write_addr;
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wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_read_addr;
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assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
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assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
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// ==============================================
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// State Machine
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// ==============================================
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reg [2:0] state;
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localparam S_IDLE = 3'b000;
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localparam S_ACCUMULATE = 3'b001;
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localparam S_PRE_READ = 3'b101;
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localparam S_LOAD_FFT = 3'b010;
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localparam S_FFT_WAIT = 3'b011;
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localparam S_OUTPUT = 3'b100;
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// Frame sync detection
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reg new_chirp_frame_d1;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) new_chirp_frame_d1 <= 0;
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else new_chirp_frame_d1 <= new_chirp_frame;
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end
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wire frame_start_pulse = new_chirp_frame & ~new_chirp_frame_d1;
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// ==============================================
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// Main State Machine
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// ==============================================
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reg [4:0] fft_sample_counter; // Reduced: only need 0..17 for 16-pt FFT
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reg [9:0] processing_timeout;
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// Memory write enable and data signals
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reg mem_we;
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reg [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_waddr_r;
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reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
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// Memory read data
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reg [DATA_WIDTH-1:0] mem_rdata_i, mem_rdata_q;
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`ifdef FORMAL
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assign fv_state = state;
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assign fv_mem_write_addr = mem_write_addr;
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assign fv_mem_read_addr = mem_read_addr;
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assign fv_write_range_bin = write_range_bin;
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assign fv_write_chirp_index = write_chirp_index;
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assign fv_read_range_bin = read_range_bin;
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assign fv_read_doppler_index = read_doppler_index;
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assign fv_processing_timeout = processing_timeout;
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assign fv_frame_buffer_full = frame_buffer_full;
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assign fv_mem_we = mem_we;
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assign fv_mem_waddr_r = mem_waddr_r;
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`endif
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// ----------------------------------------------------------
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// Separate always block for memory writes — NO async reset
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// ----------------------------------------------------------
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always @(posedge clk) begin
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if (mem_we) begin
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doppler_i_mem[mem_waddr_r] <= mem_wdata_i;
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doppler_q_mem[mem_waddr_r] <= mem_wdata_q;
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end
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mem_rdata_i <= doppler_i_mem[mem_read_addr];
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mem_rdata_q <= doppler_q_mem[mem_read_addr];
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end
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// ----------------------------------------------------------
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// Block 1: FSM / Control — async reset
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// ----------------------------------------------------------
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= S_IDLE;
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write_range_bin <= 0;
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write_chirp_index <= 0;
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frame_buffer_full <= 0;
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doppler_valid <= 0;
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fft_start <= 0;
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fft_input_valid <= 0;
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fft_input_last <= 0;
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fft_sample_counter <= 0;
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processing_timeout <= 0;
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status <= 0;
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chirps_received <= 0;
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chirp_state <= 0;
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doppler_output <= 0;
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doppler_bin <= 0;
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range_bin <= 0;
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sub_frame <= 0;
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current_sub_frame <= 0;
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end else begin
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doppler_valid <= 0;
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fft_input_valid <= 0;
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fft_input_last <= 0;
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if (processing_timeout > 0) begin
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processing_timeout <= processing_timeout - 1;
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end
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case (state)
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S_IDLE: begin
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if (frame_start_pulse) begin
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write_chirp_index <= 0;
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write_range_bin <= 0;
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frame_buffer_full <= 0;
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chirps_received <= 0;
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end
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if (data_valid && !frame_buffer_full) begin
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state <= S_ACCUMULATE;
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write_range_bin <= 1;
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end
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end
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S_ACCUMULATE: begin
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if (data_valid) begin
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if (write_range_bin < RANGE_BINS - 1) begin
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write_range_bin <= write_range_bin + 1;
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end else begin
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write_range_bin <= 0;
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write_chirp_index <= write_chirp_index + 1;
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chirps_received <= chirps_received + 1;
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if (write_chirp_index >= CHIRPS_PER_FRAME - 1) begin
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frame_buffer_full <= 1;
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chirp_state <= 0;
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state <= S_PRE_READ;
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fft_sample_counter <= 0;
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write_chirp_index <= 0;
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write_range_bin <= 0;
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// Start with sub-frame 0 (long PRI chirps 0..15)
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current_sub_frame <= 0;
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end
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end
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end
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end
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S_PRE_READ: begin
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// Prime BRAM pipeline for current sub-frame
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// read_doppler_index already set in Block 2 to sub-frame base
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fft_start <= 1;
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state <= S_LOAD_FFT;
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end
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S_LOAD_FFT: begin
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fft_start <= 0;
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// Pipeline: 2 priming cycles + CHIRPS_PER_SUBFRAME data cycles
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if (fft_sample_counter <= 1) begin
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fft_sample_counter <= fft_sample_counter + 1;
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end else if (fft_sample_counter <= CHIRPS_PER_SUBFRAME + 1) begin
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fft_input_valid <= 1;
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if (fft_sample_counter == CHIRPS_PER_SUBFRAME + 1) begin
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fft_input_last <= 1;
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state <= S_FFT_WAIT;
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fft_sample_counter <= 0;
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processing_timeout <= 1000;
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end else begin
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fft_sample_counter <= fft_sample_counter + 1;
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end
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end
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end
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S_FFT_WAIT: begin
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if (fft_output_valid) begin
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doppler_output <= {fft_output_q[15:0], fft_output_i[15:0]};
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// Pack: {sub_frame, bin[3:0]}
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doppler_bin <= {current_sub_frame, fft_sample_counter[3:0]};
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range_bin <= read_range_bin;
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sub_frame <= current_sub_frame;
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doppler_valid <= 1;
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fft_sample_counter <= fft_sample_counter + 1;
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if (fft_output_last) begin
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state <= S_OUTPUT;
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fft_sample_counter <= 0;
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end
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end
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if (processing_timeout == 0) begin
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state <= S_OUTPUT;
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end
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end
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S_OUTPUT: begin
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if (current_sub_frame == 0) begin
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// Just finished long PRI sub-frame — now do short PRI
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current_sub_frame <= 1;
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fft_sample_counter <= 0;
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state <= S_PRE_READ;
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// read_range_bin stays the same, read_doppler_index
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// will be set to CHIRPS_PER_SUBFRAME in Block 2
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end else begin
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// Finished both sub-frames for this range bin
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current_sub_frame <= 0;
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if (read_range_bin < RANGE_BINS - 1) begin
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fft_sample_counter <= 0;
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state <= S_PRE_READ;
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// read_range_bin incremented in Block 2
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end else begin
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state <= S_IDLE;
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frame_buffer_full <= 0;
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end
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end
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end
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endcase
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status <= {state, frame_buffer_full};
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end
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end
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// ----------------------------------------------------------
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// Block 2: BRAM address/data & DSP datapath — synchronous reset
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// ----------------------------------------------------------
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always @(posedge clk) begin
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if (!reset_n) begin
|
|
mem_we <= 0;
|
|
mem_waddr_r <= 0;
|
|
mem_wdata_i <= 0;
|
|
mem_wdata_q <= 0;
|
|
mult_i <= 0;
|
|
mult_q <= 0;
|
|
mult_i_raw <= 0;
|
|
mult_q_raw <= 0;
|
|
window_val_reg <= 0;
|
|
fft_input_i <= 0;
|
|
fft_input_q <= 0;
|
|
read_range_bin <= 0;
|
|
read_doppler_index <= 0;
|
|
end else begin
|
|
mem_we <= 0;
|
|
|
|
case (state)
|
|
S_IDLE: begin
|
|
if (data_valid && !frame_buffer_full) begin
|
|
mem_we <= 1;
|
|
mem_waddr_r <= mem_write_addr;
|
|
mem_wdata_i <= range_data[15:0];
|
|
mem_wdata_q <= range_data[31:16];
|
|
end
|
|
end
|
|
|
|
S_ACCUMULATE: begin
|
|
if (data_valid) begin
|
|
mem_we <= 1;
|
|
mem_waddr_r <= mem_write_addr;
|
|
mem_wdata_i <= range_data[15:0];
|
|
mem_wdata_q <= range_data[31:16];
|
|
|
|
if (write_range_bin >= RANGE_BINS - 1 &&
|
|
write_chirp_index >= CHIRPS_PER_FRAME - 1) begin
|
|
read_range_bin <= 0;
|
|
// Start reading from chirp 0 (long PRI sub-frame)
|
|
read_doppler_index <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_PRE_READ: begin
|
|
// Set read_doppler_index to first chirp of current sub-frame + 1
|
|
// (because address is presented this cycle, data arrives next)
|
|
if (current_sub_frame == 0)
|
|
read_doppler_index <= 1; // Long PRI: chirps 0..15
|
|
else
|
|
read_doppler_index <= CHIRPS_PER_SUBFRAME + 1; // Short PRI: chirps 16..31
|
|
|
|
// BREG priming: window coeff for sample 0
|
|
window_val_reg <= $signed(window_coeff[0]);
|
|
end
|
|
|
|
S_LOAD_FFT: begin
|
|
if (fft_sample_counter == 0) begin
|
|
// Pipe stage 1: multiply using pre-registered BREG value
|
|
mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
|
|
mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
|
|
window_val_reg <= $signed(window_coeff[1]);
|
|
// Advance to chirp base+2
|
|
if (current_sub_frame == 0)
|
|
read_doppler_index <= (2 < CHIRPS_PER_SUBFRAME) ? 2
|
|
: CHIRPS_PER_SUBFRAME - 1;
|
|
else
|
|
read_doppler_index <= (CHIRPS_PER_SUBFRAME + 2 < CHIRPS_PER_FRAME)
|
|
? CHIRPS_PER_SUBFRAME + 2
|
|
: CHIRPS_PER_FRAME - 1;
|
|
end else if (fft_sample_counter == 1) begin
|
|
mult_i <= mult_i_raw;
|
|
mult_q <= mult_q_raw;
|
|
mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
|
|
mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
|
|
if (2 < CHIRPS_PER_SUBFRAME)
|
|
window_val_reg <= $signed(window_coeff[2]);
|
|
// Advance to chirp base+3
|
|
begin : advance_chirp3
|
|
reg [4:0] next_chirp;
|
|
next_chirp = (current_sub_frame == 0) ? 3 : CHIRPS_PER_SUBFRAME + 3;
|
|
if (next_chirp < CHIRPS_PER_FRAME)
|
|
read_doppler_index <= next_chirp;
|
|
else
|
|
read_doppler_index <= CHIRPS_PER_FRAME - 1;
|
|
end
|
|
end else if (fft_sample_counter <= CHIRPS_PER_SUBFRAME + 1) begin
|
|
// Steady state
|
|
fft_input_i <= (mult_i + (1 << 14)) >>> 15;
|
|
fft_input_q <= (mult_q + (1 << 14)) >>> 15;
|
|
mult_i <= mult_i_raw;
|
|
mult_q <= mult_q_raw;
|
|
|
|
if (fft_sample_counter <= CHIRPS_PER_SUBFRAME - 1) begin
|
|
mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
|
|
mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
|
|
// Window coeff index within sub-frame
|
|
begin : advance_window
|
|
reg [4:0] win_idx;
|
|
win_idx = fft_sample_counter[3:0] + 1;
|
|
if (win_idx < CHIRPS_PER_SUBFRAME)
|
|
window_val_reg <= $signed(window_coeff[win_idx]);
|
|
end
|
|
// Advance BRAM read
|
|
begin : advance_bram
|
|
reg [4:0] chirp_offset;
|
|
reg [4:0] chirp_base;
|
|
chirp_offset = fft_sample_counter[3:0] + 2;
|
|
chirp_base = (current_sub_frame == 0) ? 0 : CHIRPS_PER_SUBFRAME;
|
|
if (chirp_base + chirp_offset < CHIRPS_PER_FRAME)
|
|
read_doppler_index <= chirp_base + chirp_offset;
|
|
else
|
|
read_doppler_index <= CHIRPS_PER_FRAME - 1;
|
|
end
|
|
end
|
|
|
|
if (fft_sample_counter == CHIRPS_PER_SUBFRAME + 1) begin
|
|
// Reset read index for potential next operation
|
|
if (current_sub_frame == 0)
|
|
read_doppler_index <= CHIRPS_PER_SUBFRAME; // Ready for short sub-frame
|
|
else
|
|
read_doppler_index <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_OUTPUT: begin
|
|
if (current_sub_frame == 0) begin
|
|
// Transitioning to short PRI sub-frame
|
|
// Set read_doppler_index to start of short sub-frame
|
|
read_doppler_index <= CHIRPS_PER_SUBFRAME;
|
|
end else begin
|
|
// Both sub-frames done
|
|
if (read_range_bin < RANGE_BINS - 1) begin
|
|
read_range_bin <= read_range_bin + 1;
|
|
read_doppler_index <= 0; // Next range bin starts with long sub-frame
|
|
end
|
|
end
|
|
end
|
|
|
|
default: begin
|
|
// S_FFT_WAIT: no BRAM-write or address operations needed
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// ==============================================
|
|
// FFT Module — 16-point
|
|
// ==============================================
|
|
xfft_16 fft_inst (
|
|
.aclk(clk),
|
|
.aresetn(reset_n),
|
|
.s_axis_config_tdata(8'h01),
|
|
.s_axis_config_tvalid(fft_start),
|
|
.s_axis_config_tready(fft_ready),
|
|
.s_axis_data_tdata({fft_input_q, fft_input_i}),
|
|
.s_axis_data_tvalid(fft_input_valid),
|
|
.s_axis_data_tlast(fft_input_last),
|
|
.m_axis_data_tdata({fft_output_q, fft_output_i}),
|
|
.m_axis_data_tvalid(fft_output_valid),
|
|
.m_axis_data_tlast(fft_output_last),
|
|
.m_axis_data_tready(1'b1)
|
|
);
|
|
|
|
// ==============================================
|
|
// Status Outputs
|
|
// ==============================================
|
|
assign processing_active = (state != S_IDLE);
|
|
// NOTE: frame_complete is a LEVEL, not a pulse. It is high whenever the
|
|
// doppler processor is idle with no buffered frame. radar_receiver_final.v
|
|
// converts this to a single-cycle rising-edge pulse before routing to
|
|
// downstream consumers (USB FT2232H, AGC, CFAR). Do NOT connect this
|
|
// level output directly to modules that expect a pulse.
|
|
assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
|
|
|
|
endmodule
|