853d2a5fd9
Pre-fix Tests 1/2/4 in fpga_self_test.v gave false PASS even on broken
silicon:
S-19 Test 1 (CIC): `result_flags[1] <= 1'b1` unconditional, comment
admitted "always true for simple check".
S-20 Test 2 (FFT): `(16'sd100+16'sd100 == 16'sd200) && (...)` —
both predicates compile-time-fold to 1; synth reduces to a
constant write.
S-21 Test 4 (ADC): PASS once N samples land, regardless of value.
A stuck-at-0 / stuck-at-MAX / dead LVDS link still PASSed
provided adc_valid_in toggled.
Fixes:
Test 1: drive impulse {5,0,0,0,0,0,0} through registered integrator
y[n]=y[n-1]+x[n]; require accumulator==5 after step
response. Real adder + register path; sign-extension
exercised. Detail = 0xC1 on fail.
Test 2: real radix-2 butterfly with twiddle multiply across 4 FSM
states. A=8, B=4 (real), W=2+3j -> WB=(8,12), A'=(16,12),
B'=(0,-12). Forces synth to instantiate signed multiplier
(DSP slice) + 17-bit signed add/sub. Detail = 0xF2 on fail.
Test 4: track min/max across 256-sample capture, require
(max - min) > ADC_RANGE_THRESHOLD (10 LSB). Catches stuck-at
faults. Does NOT distinguish AD9484 format mismatches
(audit's per-mode mean check requires SPI, impossible per
AUDIT-C13). Detail = 0xAD on fail.
Tests:
- tb_fpga_self_test.v existing Group 1-4 (16 PASS) still pass: varied
ADC counter input gives range >> 10.
- New Group 5: drive constant 0 -> expect Test 4 FAIL + detail=0xAD.
- New Group 6: drive constant 0x7FFF -> expect Test 4 FAIL + detail=0xAD.
- Regression: 41/41 PASS; fpga_self_test 22/22 (was 16/16).
421 lines
17 KiB
Verilog
421 lines
17 KiB
Verilog
`timescale 1ns / 1ps
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// fpga_self_test.v — Board Bring-Up Smoke Test Controller
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//
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// Triggered by host opcode 0x30. Exercises each subsystem independently:
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// Test 0: BRAM write/read pattern (walking 1s)
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// Test 1: CIC impulse response check (known input → expected output)
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// Test 2: FFT known-input test (DC input → bin 0 peak)
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// Test 3: Arithmetic / saturating-add check
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// Test 4: ADC raw data capture (dump N samples to host)
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//
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// Results reported back via a status register readable by host (opcode 0x31).
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// Each test produces a PASS/FAIL bit in result_flags[4:0].
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//
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// Integration: radar_system_top.v wires host_self_test_trigger (from opcode 0x30)
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// to this module's `trigger` input, and reads `result_flags` / `result_valid`
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// via opcode 0x31.
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//
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// Resource cost: ~200 LUTs, 1 BRAM (test pattern), 0 DSP.
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module fpga_self_test (
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input wire clk,
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input wire reset_n,
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// Control
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input wire trigger, // 1-cycle pulse from host (opcode 0x30)
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output reg busy, // High while tests are running
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output reg result_valid, // Pulses when all tests complete
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output reg [4:0] result_flags, // Per-test PASS(1)/FAIL(0)
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output reg [7:0] result_detail, // Diagnostic detail (first failing test ID + info)
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// ADC raw capture interface (active during Test 4)
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input wire [15:0] adc_data_in, // Raw ADC sample (from ad9484_interface)
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input wire adc_valid_in, // ADC sample valid
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output reg capture_active, // High during ADC capture window
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output reg [15:0] capture_data, // Captured ADC sample for USB readout
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output reg capture_valid // Pulse: new captured sample available
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);
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// ============================================================================
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// FSM States
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// ============================================================================
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localparam [3:0] ST_IDLE = 4'd0,
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ST_BRAM_WR = 4'd1,
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ST_BRAM_GAP = 4'd2, // 1-cycle gap: let last write complete
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ST_BRAM_RD = 4'd3,
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ST_BRAM_CHK = 4'd4,
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ST_CIC_SETUP = 4'd5,
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ST_CIC_CHECK = 4'd6,
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ST_FFT_SETUP = 4'd7,
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ST_FFT_CHECK = 4'd8,
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ST_ARITH = 4'd9,
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ST_ADC_CAP = 4'd10,
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ST_DONE = 4'd11;
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reg [3:0] state;
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// ============================================================================
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// Test 0: BRAM Write/Read Pattern
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// ============================================================================
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// Uses a small embedded BRAM (64×16) with walking-1 pattern.
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localparam BRAM_DEPTH = 64;
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localparam BRAM_AW = 6;
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reg [15:0] test_bram [0:BRAM_DEPTH-1];
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reg [BRAM_AW-1:0] bram_addr;
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reg [15:0] bram_wr_data;
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reg [15:0] bram_rd_data;
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reg bram_pass;
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// Synchronous BRAM write — use walking_one directly to avoid pipeline lag
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always @(posedge clk) begin
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if (state == ST_BRAM_WR)
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test_bram[bram_addr] <= walking_one(bram_addr);
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end
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// Synchronous BRAM read (1-cycle latency)
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always @(posedge clk) begin
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bram_rd_data <= test_bram[bram_addr];
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end
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// Walking-1 pattern: address → (1 << (addr % 16))
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function [15:0] walking_one;
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input [BRAM_AW-1:0] addr;
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begin
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walking_one = 16'd1 << (addr[3:0]);
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end
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endfunction
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// ============================================================================
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// Test 3: Arithmetic Check
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// ============================================================================
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// Verify saturating signed add (same logic as mti_canceller.v)
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function [15:0] sat_add;
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input signed [15:0] a;
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input signed [15:0] b;
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reg signed [16:0] sum_full;
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begin
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sum_full = {a[15], a} + {b[15], b};
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if (sum_full > 17'sd32767)
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sat_add = 16'sd32767;
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else if (sum_full < -17'sd32768)
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sat_add = -16'sd32768;
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else
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sat_add = sum_full[15:0];
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end
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endfunction
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reg arith_pass;
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// ============================================================================
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// Counter / Control
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// ============================================================================
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reg [9:0] step_cnt; // General-purpose step counter (up to 1024)
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reg [9:0] adc_cap_cnt;
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localparam ADC_CAP_SAMPLES = 256; // Number of raw ADC samples to capture
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// Pipeline register for BRAM read verification (accounts for 1-cycle read latency)
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reg [BRAM_AW-1:0] bram_rd_addr_d;
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reg bram_rd_valid;
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// ============================================================================
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// AUDIT-S19/S20/S21: real Test 1/2/4 state (replaces pre-fix tautologies)
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// ============================================================================
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// Test 1 (CIC integrator impulse response)
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reg signed [31:0] cic_accum;
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reg signed [15:0] cic_input;
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// Test 2 (radix-2 butterfly with complex twiddle)
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reg signed [15:0] fft_a_re, fft_b_re, fft_w_re, fft_w_im;
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reg signed [31:0] fft_wb_re, fft_wb_im;
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reg signed [16:0] fft_aprime_re, fft_aprime_im;
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reg signed [16:0] fft_bprime_re, fft_bprime_im;
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// Test 4 (ADC activity check — min/max over capture window)
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reg signed [15:0] adc_min, adc_max;
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localparam signed [15:0] ADC_RANGE_THRESHOLD = 16'sd10;
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// ============================================================================
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// Main FSM
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= ST_IDLE;
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busy <= 1'b0;
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result_valid <= 1'b0;
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result_flags <= 5'b00000;
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result_detail <= 8'd0;
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bram_addr <= 0;
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bram_wr_data <= 16'd0;
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bram_pass <= 1'b1;
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arith_pass <= 1'b1;
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step_cnt <= 0;
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capture_active <= 1'b0;
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capture_data <= 16'd0;
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capture_valid <= 1'b0;
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adc_cap_cnt <= 0;
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bram_rd_addr_d <= 0;
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bram_rd_valid <= 1'b0;
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// AUDIT-S19/S20/S21
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cic_accum <= 32'sd0;
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cic_input <= 16'sd0;
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fft_a_re <= 16'sd0;
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fft_b_re <= 16'sd0;
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fft_w_re <= 16'sd0;
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fft_w_im <= 16'sd0;
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fft_wb_re <= 32'sd0;
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fft_wb_im <= 32'sd0;
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fft_aprime_re <= 17'sd0;
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fft_aprime_im <= 17'sd0;
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fft_bprime_re <= 17'sd0;
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fft_bprime_im <= 17'sd0;
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adc_min <= 16'sd0;
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adc_max <= 16'sd0;
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end else begin
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// Default one-shot signals
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result_valid <= 1'b0;
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capture_valid <= 1'b0;
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bram_rd_valid <= 1'b0;
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case (state)
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// ============================================================
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// IDLE: Wait for trigger
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// ============================================================
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ST_IDLE: begin
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if (trigger) begin
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busy <= 1'b1;
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result_flags <= 5'b00000;
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result_detail <= 8'd0;
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bram_pass <= 1'b1;
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arith_pass <= 1'b1;
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bram_addr <= 0;
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step_cnt <= 0;
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state <= ST_BRAM_WR;
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end
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end
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// ============================================================
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// Test 0: BRAM Write Phase — write walking-1 pattern
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// ============================================================
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ST_BRAM_WR: begin
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if (bram_addr == BRAM_DEPTH - 1) begin
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bram_addr <= 0;
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state <= ST_BRAM_GAP;
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end else begin
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bram_addr <= bram_addr + 1;
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end
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end
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// 1-cycle gap: ensures last BRAM write completes before reads begin
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ST_BRAM_GAP: begin
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bram_addr <= 0;
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state <= ST_BRAM_RD;
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end
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// ============================================================
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// Test 0: BRAM Read Phase — issue reads
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// ============================================================
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ST_BRAM_RD: begin
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// BRAM read has 1-cycle latency: issue address, check next cycle
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bram_rd_addr_d <= bram_addr;
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bram_rd_valid <= 1'b1;
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if (bram_addr == BRAM_DEPTH - 1) begin
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state <= ST_BRAM_CHK;
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end else begin
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bram_addr <= bram_addr + 1;
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end
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end
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// ============================================================
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// Test 0: BRAM Check — verify last read, finalize
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// ============================================================
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ST_BRAM_CHK: begin
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// Check final read (pipeline delay)
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if (bram_rd_data != walking_one(bram_rd_addr_d)) begin
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bram_pass <= 1'b0;
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result_detail <= {4'd0, bram_rd_addr_d[3:0]};
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end
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result_flags[0] <= bram_pass;
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state <= ST_CIC_SETUP;
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step_cnt <= 0;
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end
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// ============================================================
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// Test 1: CIC integrator impulse response (AUDIT-S19 fix)
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// ============================================================
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// Pre-fix this state set `result_flags[1] <= 1'b1` unconditionally
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// ("always true for simple check") so a broken integrator path on
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// the silicon would still PASS. Now drives a real impulse {5,0,0,...}
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// through y[n] = y[n-1] + x[n] and checks the registered accumulator
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// value at the end. Catches stuck-at, broken adder, or sign-extension
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// bug in the arithmetic path.
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ST_CIC_SETUP: begin
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if (step_cnt == 0) begin
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cic_accum <= 32'sd0;
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cic_input <= 16'sd5; // impulse value
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step_cnt <= 1;
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end else if (step_cnt < 8) begin
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cic_accum <= cic_accum +
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{{16{cic_input[15]}}, cic_input}; // sign-extend
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cic_input <= 16'sd0; // zero-pad after impulse
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step_cnt <= step_cnt + 1;
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end else begin
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// After impulse + 6 zeros, integrator holds at 5 (step response)
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if (cic_accum == 32'sd5) begin
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result_flags[1] <= 1'b1;
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end else begin
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result_flags[1] <= 1'b0;
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result_detail <= 8'hC1; // CIC fail marker
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end
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state <= ST_FFT_SETUP;
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step_cnt <= 0;
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end
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end
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// ============================================================
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// Test 2: Radix-2 butterfly with twiddle multiply (AUDIT-S20 fix)
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// ============================================================
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// Pre-fix this evaluated `(16'sd100+16'sd100 == 16'sd200) &&
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// (16'sd100-16'sd100 == 16'sd0)` — both predicates compile-time-fold
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// to 1'b1, so synth reduces the whole test to `result_flags[2] <= 1'b1`.
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// Replaced with a real radix-2 butterfly that exercises signed
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// multiplications + adds across multiple FSM states with register
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// dataflow (synth must instantiate DSP/multiplier resources).
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//
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// Inputs: A = 8 (real), B = 4 (real), W = 2 + 3j
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// Step 1: WB = W*B (with B_im=0, so only 2 mults)
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// WB_re = W_re * B_re = 2 * 4 = 8
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// WB_im = W_im * B_re = 3 * 4 = 12
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// Step 2: Butterfly:
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// A' = A + WB = (8+8, 0+12) = (16, 12)
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// B' = A - WB = (8-8, 0-12) = (0, -12)
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// Step 3: Compare against golden.
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ST_FFT_SETUP: begin
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if (step_cnt == 0) begin
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fft_a_re <= 16'sd8;
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fft_b_re <= 16'sd4;
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fft_w_re <= 16'sd2;
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fft_w_im <= 16'sd3;
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step_cnt <= 1;
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end else if (step_cnt == 1) begin
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fft_wb_re <= fft_w_re * fft_b_re; // 2*4 = 8
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fft_wb_im <= fft_w_im * fft_b_re; // 3*4 = 12
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step_cnt <= 2;
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end else if (step_cnt == 2) begin
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fft_aprime_re <= {fft_a_re[15], fft_a_re} + fft_wb_re[16:0];
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fft_aprime_im <= 17'sd0 + fft_wb_im[16:0];
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fft_bprime_re <= {fft_a_re[15], fft_a_re} - fft_wb_re[16:0];
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fft_bprime_im <= 17'sd0 - fft_wb_im[16:0];
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step_cnt <= 3;
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end else begin
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if (fft_aprime_re == 17'sd16 && fft_aprime_im == 17'sd12 &&
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fft_bprime_re == 17'sd0 && fft_bprime_im == -17'sd12) begin
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result_flags[2] <= 1'b1;
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end else begin
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result_flags[2] <= 1'b0;
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result_detail <= 8'hF2; // FFT fail marker
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end
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state <= ST_ARITH;
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step_cnt <= 0;
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end
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end
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// ============================================================
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// Test 3: Saturating Arithmetic
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// ============================================================
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ST_ARITH: begin
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// Test cases for sat_add:
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// 32767 + 1 should saturate to 32767 (not wrap to -32768)
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// -32768 + (-1) should saturate to -32768
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// 100 + 200 = 300
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if (step_cnt == 0) begin
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if (sat_add(16'sd32767, 16'sd1) != 16'sd32767)
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arith_pass <= 1'b0;
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step_cnt <= 1;
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end else if (step_cnt == 1) begin
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if (sat_add(-16'sd32768, -16'sd1) != -16'sd32768)
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arith_pass <= 1'b0;
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step_cnt <= 2;
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end else if (step_cnt == 2) begin
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if (sat_add(16'sd100, 16'sd200) != 16'sd300)
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arith_pass <= 1'b0;
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step_cnt <= 3;
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end else begin
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result_flags[3] <= arith_pass;
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state <= ST_ADC_CAP;
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step_cnt <= 0;
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adc_cap_cnt <= 0;
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end
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end
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// ============================================================
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// Test 4: ADC activity (min/max range) check (AUDIT-S21 fix)
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// ============================================================
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// Pre-fix this set `result_flags[4] <= 1'b1` once N samples were
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// observed, regardless of value. A stuck-at-0 ADC (broken LVDS link,
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// wrong AD9484 mode per AUDIT-C3, dead sample-and-hold) would still
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// PASS as long as adc_valid_in toggled. Now tracks min/max across the
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// capture window and requires range > ADC_RANGE_THRESHOLD (10 LSB).
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// Catches stuck-at faults; does NOT distinguish AD9484 format
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// mismatches (audit's per-mode mean check requires AD9484 SPI which
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// is impossible on production HW per AUDIT-C13).
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ST_ADC_CAP: begin
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capture_active <= 1'b1;
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if (adc_valid_in) begin
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capture_data <= adc_data_in;
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capture_valid <= 1'b1;
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// Activity tracking: seed min/max on first sample, then update
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if (adc_cap_cnt == 0) begin
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adc_min <= adc_data_in;
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adc_max <= adc_data_in;
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end else begin
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if ($signed(adc_data_in) < $signed(adc_min)) adc_min <= adc_data_in;
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if ($signed(adc_data_in) > $signed(adc_max)) adc_max <= adc_data_in;
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end
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adc_cap_cnt <= adc_cap_cnt + 1;
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if (adc_cap_cnt >= ADC_CAP_SAMPLES - 1) begin
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// PASS if observed range exceeds stuck-at threshold
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if (($signed(adc_max) - $signed(adc_min)) > ADC_RANGE_THRESHOLD) begin
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result_flags[4] <= 1'b1;
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end else begin
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result_flags[4] <= 1'b0;
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result_detail <= 8'hAD; // stuck-at / no-activity marker
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end
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capture_active <= 1'b0;
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state <= ST_DONE;
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end
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end
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// Timeout: if no ADC data after 1000 cycles (10 us @ 100 MHz), FAIL
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step_cnt <= step_cnt + 1;
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if (step_cnt >= 10'd1000 && adc_cap_cnt == 0) begin
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result_flags[4] <= 1'b0;
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result_detail <= 8'hAD; // ADC timeout marker
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capture_active <= 1'b0;
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state <= ST_DONE;
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end
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end
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||
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||
// ============================================================
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// DONE: Report results
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||
// ============================================================
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||
ST_DONE: begin
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busy <= 1'b0;
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result_valid <= 1'b1;
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state <= ST_IDLE;
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end
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||
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||
default: state <= ST_IDLE;
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||
endcase
|
||
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||
// Pipeline: check BRAM read data vs expected (during ST_BRAM_RD)
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||
if (bram_rd_valid) begin
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||
if (bram_rd_data != walking_one(bram_rd_addr_d)) begin
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bram_pass <= 1'b0;
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result_detail <= {4'd0, bram_rd_addr_d[3:0]};
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end
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end
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end
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end
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endmodule
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