6738f12e54
Stage-7 ADC chain audit. The MMCM SIMULATION model in adc_clk_mmcm.v takes 4096 DCO cycles (~10 µs at 400 MHz) to assert mmcm_locked. The existing TB waited only ~5 cycles after each reset deassert, so the gated reset_n_400m never released and adc_data_valid_400m stayed low for every test group past the initial reset checks. Expose mmcm_locked as a new module output on ad9484_interface_400m (real path) and ad9484_interface_400m_stub (sim path; tied high one DCO cycle after reset deassert since the stub has no MMCM). Connect it through to tb_ad9484_xsim.v and add a `wait_for_adc_ready` task that waits on the lock signal plus 6 DCO cycles for the 2-FF lock-sync, 2-FF reset-sync, and pipeline drain. Apply the task at each of the five reset cycles in the testbench. radar_receiver_final.v: tie the new port off (.mmcm_locked()) — host status pipeline doesn't surface lock yet, deferred for a future status-word widening. Local iverilog regression (36/0/7) clean. xsim verification of the xsim-only TB itself is pending (remote Vivado host).
240 lines
10 KiB
Verilog
240 lines
10 KiB
Verilog
module ad9484_interface_400m (
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// ADC Physical Interface (LVDS)
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input wire [7:0] adc_d_p, // ADC Data P
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input wire [7:0] adc_d_n, // ADC Data N
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input wire adc_dco_p, // Data Clock Output P (400MHz)
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input wire adc_dco_n, // Data Clock Output N (400MHz)
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// Audit F-0.1: AD9484 OR (overrange) LVDS pair (SDR, like data — see
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// AUDIT-C4 note below; an earlier comment incorrectly described this as
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// DDR). Routed on the 50T main board to bank 14 pins M6/N6. Asserts for
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// any sample whose absolute value exceeds full-scale.
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input wire adc_or_p,
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input wire adc_or_n,
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// System Interface
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input wire sys_clk, // 100MHz system clock (for control only)
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input wire reset_n,
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// Output at 400MHz domain
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output wire [7:0] adc_data_400m, // ADC data at 400MHz
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output wire adc_data_valid_400m, // Valid at 400MHz
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output wire adc_dco_bufg, // Buffered 400MHz DCO clock for downstream use
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// Audit F-0.1: OR flag, clk_400m domain. High on any sample in the
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// current 400 MHz cycle where the ADC reports overrange.
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output wire adc_overrange_400m,
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// Audit F-7.4: MMCM lock indicator. Surfaces the internal mmcm_locked
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// wire so testbenches (and, in future, the host status pipeline) can
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// gate on a stable jitter-cleaned 400 MHz clock instead of guessing at
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// a fixed wait. Combinational MMCME2 output — synchronize before use
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// outside the clk_400m domain.
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output wire mmcm_locked
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);
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// LVDS to single-ended conversion
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wire [7:0] adc_data;
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wire adc_dco;
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// IBUFDS for each data bit
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// NOTE: IOSTANDARD and DIFF_TERM are set via XDC constraints, not RTL
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// parameters, to support multiple FPGA targets with different bank voltages:
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// - XC7A200T (FBG484): Bank 14 VCCO = 2.5V → LVDS_25
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// - XC7A50T (FTG256): Bank 14 VCCO = 3.3V → LVDS_33
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genvar i;
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generate
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for (i = 0; i < 8; i = i + 1) begin : data_buffers
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IBUFDS #(
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.DIFF_TERM("FALSE"), // Overridden by XDC DIFF_TERM property
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.IOSTANDARD("DEFAULT") // Overridden by XDC IOSTANDARD property
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) ibufds_data (
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.O(adc_data[i]),
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.I(adc_d_p[i]),
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.IB(adc_d_n[i])
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);
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end
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endgenerate
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// IBUFDS for DCO
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IBUFDS #(
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.DIFF_TERM("FALSE"), // Overridden by XDC DIFF_TERM property
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.IOSTANDARD("DEFAULT") // Overridden by XDC IOSTANDARD property
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) ibufds_dco (
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.O(adc_dco),
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.I(adc_dco_p),
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.IB(adc_dco_n)
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);
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// ============================================================================
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// Clock buffering strategy for source-synchronous ADC interface:
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//
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// BUFIO: Near-zero insertion delay, drives IOB primitives only (in this
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// module: the IOB-packed input FF on each data bit and the OR pair).
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// Eliminates the hold violation that a BUFG-clocked capture would
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// suffer from BUFG insertion delay.
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//
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// BUFG: Global clock buffer for fabric logic (downstream processing and
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// the BUFIO→BUFG re-register stage). ~4 ns insertion delay, fine
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// for fabric-to-fabric paths.
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// ============================================================================
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wire adc_dco_bufio; // Near-zero delay — drives IOB IFFs only
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wire adc_dco_buffered; // BUFG output — drives fabric logic
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BUFIO bufio_dco (
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.I(adc_dco),
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.O(adc_dco_bufio)
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);
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// MMCME2 jitter-cleaning wrapper replaces the direct BUFG.
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// The PLL feedback loop attenuates input jitter from ~50 ps to ~20-30 ps,
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// reducing clock uncertainty and improving WNS on the 400 MHz CIC path.
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// Audit F-7.4: mmcm_locked is now exposed as a module output — see the
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// port-list comment above.
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wire mmcm_locked_int;
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adc_clk_mmcm mmcm_inst (
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.clk_in (adc_dco), // 400 MHz from IBUFDS output
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.reset_n (reset_n),
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.clk_400m_out (adc_dco_buffered), // Jitter-cleaned 400 MHz on BUFG
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.mmcm_locked (mmcm_locked_int)
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);
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assign adc_dco_bufg = adc_dco_buffered;
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assign mmcm_locked = mmcm_locked_int;
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// AUDIT-C4 (2026-05-01): AD9484 outputs SDR LVDS (datasheet p.5: "Output
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// (LVDS—SDR)"; p.16: "data outputs are valid on the rising edge of DCO").
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// One new sample per DCO period (DCO=fs=400 MHz); data is held stable for
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// the full period. The chip has no DDR mode and no SPI access (CSB tied
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// high on the production board, see Main_Board.sch:46719) so no register
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// can change this.
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//
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// Capture on the FALLING DCO edge — 1.25 ns inside AD9484's stable data
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// window. The rising DCO edge coincides with the AD9484 data transition
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// (tSKEW = ±70 ps vs typical IFF setup ~150 ps), which would be
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// functionally metastable; the falling edge has ~0.4 ns of setup margin
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// against tPD = 0.85 ns. IOB=TRUE forces the FF into the input I/O block,
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// giving near-zero clock-to-Q insertion delay matched to BUFIO.
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//
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// Previous (broken) behaviour: an IDDR captured both edges and a `dco_phase`
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// FSM alternated Q1/Q2 in an attempt to demux a "DDR" stream. Because the
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// chip is SDR, both edges represent the same sample, and the alternation
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// produced approximately [s_{-1}, s_1, s_1, s_3, s_3, …] — odd-sample
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// duplication with even-sample loss, equivalent to decimate-by-2 +
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// ZOH upsample-by-2. The downstream 120 MHz IF then folded to ~80 MHz
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// and corrupted the DDC. See git log for the audit trail.
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(* IOB = "TRUE" *) reg [7:0] adc_data_iff;
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always @(negedge adc_dco_bufio) begin
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adc_data_iff <= adc_data;
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end
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// ============================================================================
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// Re-register the IFF output into the BUFG domain
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// adc_data_iff is stable from one falling DCO edge to the next (full DCO
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// period of validity), so the rising-edge BUFG capture has ample margin.
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// BUFIO and BUFG are derived from the same source (adc_dco), so they are
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// frequency-matched.
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// ============================================================================
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// Timing on the BUFIO→BUFG CDC edge is governed by a 3.000 ns
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// set_max_delay in constraints/adc_clk_mmcm.xdc (1.2× the 2.500 ns period),
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// which leaves the placer free and still fits inside the ADC data-valid
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// window. The fabric BUFG-clocked re-register intentionally lives outside
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// the IOB — packing it back into the IOB column was tried in earlier
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// builds and rejected (the BUFG clock can't share the ILOGIC clock mux
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// with a BUFIO-domain capture, and a pblock around the IDDR column
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// pulled fanout into the I/O region and caused router congestion on 51
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// unrelated paths).
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reg [7:0] adc_data_iff_bufg;
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always @(posedge adc_dco_buffered) begin
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adc_data_iff_bufg <= adc_data_iff;
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end
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// SDR output: one sample per BUFG cycle (400 MHz BUFG = 400 MSPS)
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reg [7:0] adc_data_400m_reg;
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reg adc_data_valid_400m_reg;
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// ── Reset synchronizer ────────────────────────────────────────
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// reset_n comes from the 100 MHz sys_clk domain. Assertion (going low)
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// is asynchronous and safe — the FFs enter reset instantly. De-assertion
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// (going high) must be synchronised to adc_dco_buffered to avoid
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// metastability. This is the classic "async assert, sync de-assert" pattern.
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//
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// mmcm_locked gates de-assertion: the 400 MHz domain stays in reset until
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// the MMCM PLL has locked and the jitter-cleaned clock is stable.
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// mmcm_locked is a combinational MMCME2 output and can glitch; sync it
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// into the 400 MHz domain with a 2-FF chain before using it in the
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// async-reset branch below so a LOCKED blip doesn't asynchronously
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// re-reset the domain. The chain is itself async-reset by the raw
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// reset_n so it forces reset_n_gated=0 at power-up (no valid adc_dco
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// edges exist yet to clock the sync chain).
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(* ASYNC_REG = "TRUE" *) reg [1:0] mmcm_locked_sync_400m;
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always @(posedge adc_dco_buffered or negedge reset_n) begin
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if (!reset_n)
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mmcm_locked_sync_400m <= 2'b00;
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else
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mmcm_locked_sync_400m <= {mmcm_locked_sync_400m[0], mmcm_locked};
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end
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wire mmcm_locked_400m = mmcm_locked_sync_400m[1];
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
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wire reset_n_400m;
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wire reset_n_gated = reset_n & mmcm_locked_400m;
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always @(posedge adc_dco_buffered or negedge reset_n_gated) begin
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if (!reset_n_gated)
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reset_sync_400m <= 2'b00; // async assert (or MMCM not locked)
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else
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reset_sync_400m <= {reset_sync_400m[0], 1'b1}; // sync de-assert
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end
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assign reset_n_400m = reset_sync_400m[1];
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always @(posedge adc_dco_buffered or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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adc_data_400m_reg <= 8'b0;
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adc_data_valid_400m_reg <= 1'b0;
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end else begin
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adc_data_400m_reg <= adc_data_iff_bufg;
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adc_data_valid_400m_reg <= 1'b1;
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end
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end
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assign adc_data_400m = adc_data_400m_reg;
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assign adc_data_valid_400m = adc_data_valid_400m_reg;
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// ============================================================================
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// Audit F-0.1 / AUDIT-C4: AD9484 OR (overrange) capture
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// OR is an SDR LVDS pair (per AD9484 datasheet — the chip outputs SDR,
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// not DDR; comment in earlier revision was wrong). One assertion per DCO
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// period, valid on the rising DCO edge, held stable for the rest of the
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// period. Captured at the falling DCO edge in the same IFF style as the
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// data path. Downstream stickifies in its own domain.
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// ============================================================================
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wire adc_or_raw;
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IBUFDS #(
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.DIFF_TERM("FALSE"),
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.IOSTANDARD("DEFAULT")
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) ibufds_or (
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.O(adc_or_raw),
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.I(adc_or_p),
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.IB(adc_or_n)
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);
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(* IOB = "TRUE" *) reg adc_or_iff;
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always @(negedge adc_dco_bufio) begin
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adc_or_iff <= adc_or_raw;
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end
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reg adc_or_iff_bufg;
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always @(posedge adc_dco_buffered) begin
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adc_or_iff_bufg <= adc_or_iff;
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end
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reg adc_overrange_r;
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always @(posedge adc_dco_buffered or negedge reset_n_400m) begin
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if (!reset_n_400m)
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adc_overrange_r <= 1'b0;
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else
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adc_overrange_r <= adc_or_iff_bufg;
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end
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assign adc_overrange_400m = adc_overrange_r;
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endmodule |