4238eb1b99
Drop the chirp-v1 1-bit use_long_chirp memory loader and its 6 .mem files;
introduce chirp_reference_rom — wave_sel-native, single 8192x16 BRAM array
per Q15 lane, 4-region init (SHORT, MEDIUM, LONG seg0/seg1) loaded from the
PR-B mem files. Same 1-clk read latency as the legacy module so the RX-B
autocorrelation alignment fix carries through unchanged.
Receiver-side wave_sel shim added in radar_receiver_final.v:
wire [1:0] wave_sel = use_long_chirp ? RP_WAVE_LONG : RP_WAVE_SHORT;
This is a 1-line transitional bridge while radar_mode_controller still
emits 1-bit use_long_chirp; PR-D deletes the shim and wires chirp_scheduler
straight through. MEDIUM is loaded into the ROM but unreachable through
the production path until PR-D.
BRAM cost: 8 RAMB18 (was 6 in chirp-v1). +2 BRAM is the cost of adding
MEDIUM to the waveform set; not avoidable.
Files added:
- chirp_reference_rom.v
Files removed:
- chirp_memory_loader_param.v
- long_chirp_seg{0,1}_{i,q}.mem (4 files)
- short_chirp_{i,q}.mem (2 files)
- tb/cosim/validate_mem_files.py (legacy file-set validator; replaced by
gen_chirp_mem.py's internal verify_phase_match)
- tb/cosim/analyze_short_chirp_mismatch.py (one-shot tool from the
chirp-v1 TX-I investigation; finding incorporated, references the
deleted short_chirp_*.mem files)
Files updated for module rename:
- radar_receiver_final.v — instance, comments, wave_sel shim
- radar_mode_controller.v — header comment
- matched_filter_processing_chain.v — header comment
- scripts/200t/build_200t.tcl — explicit RTL list
- run_regression.sh — 5 spots
- tb/tb_rxb_fullchain_latency.v — instance, wave_sel shim, mem filenames,
SHORT_LEN 50 → 100 (1 µs at 100 MHz)
- tb/tb_system_e2e.v — header comment
Verification:
- chirp_reference_rom standalone iverilog compile: clean
- Full receiver chain compile (21 RTL files): clean
- tb_rxb_fullchain_latency runs end-to-end with new ROM + new mem files
+ 100-sample SHORT chirp; autocorrelation peak at bin 0, peak |I|+|Q|
= 15115. Confirms 1-clk ROM read latency is preserved and the RX-B
direct-wire-with-1-FF alignment still holds.
- 50T build script (scripts/50t/build_50t.tcl) uses glob *.v — no edit
needed; it picks up the new file automatically.
122 lines
5.9 KiB
Verilog
122 lines
5.9 KiB
Verilog
`timescale 1ns / 1ps
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`include "radar_params.vh"
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// ============================================================================
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// chirp_reference_rom.v — 3-waveform matched-filter reference ROM (RX side)
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// ============================================================================
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// Replaces the chirp-v1 chirp_memory_loader_param.v (1-bit `use_long_chirp`,
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// 6 .mem files, separate BRAMs for long/short).
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//
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// Carries one of {SHORT, MEDIUM, LONG} via wave_sel[1:0] — see RP_WAVE_*
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// in radar_params.vh. The .mem files (PR-B) are uniformly 2048 entries each
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// in Q15 I/Q hex; LONG occupies two 2048 segments; SHORT and MEDIUM each
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// occupy a single 2048 segment with internal zero-pad past the chirp end.
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//
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// BRAM layout (single 8192x16 array per lane — Vivado infers 4 RAMB18/lane,
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// 8 RAMB18 total. Same cost as chirp-v1 dual-array layout because LONG
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// already needed 4 RAMB18; folding SHORT and MEDIUM into the same address
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// space costs the 4 BRAMs we'd add for medium anyway):
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//
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// addr[12:11] region source files
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// --------- --------------------- --------------------------------
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// 2'b00 SHORT ([0..2047]) rx_short_{i,q}.mem
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// 2'b01 MEDIUM ([0..2047]) rx_medium_{i,q}.mem
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// 2'b10 LONG seg0 ([0..2047]) rx_long_seg0_{i,q}.mem
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// 2'b11 LONG seg1 ([0..2047]) rx_long_seg1_{i,q}.mem
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//
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// Read addressing:
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// case (wave_sel)
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// RP_WAVE_SHORT: full_addr = {2'b00, sample_addr}
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// RP_WAVE_MEDIUM: full_addr = {2'b01, sample_addr}
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// RP_WAVE_LONG: full_addr = {1'b1, segment_select[0], sample_addr}
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// default: (RP_WAVE_RESERVED) zero-output, mem_ready still pulses
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// endcase
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//
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// Output semantics — drop-in compatible with chirp_memory_loader_param:
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// - Synchronous read: ref_i / ref_q valid 1 clk after mem_request.
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// - mem_ready pulses with ref data (1 clk after mem_request).
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// - SAME 1-cycle latency as the legacy module (preserves RX-B autocorrelation
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// peak alignment validated by tb_rxb_fullchain_latency).
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//
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// REQP-1839/1840 compliance (BRAM output registers cannot have async resets):
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// - The BRAM read block uses a SYNCHRONOUS reset, which Vivado maps to the
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// RAMB18 RSTREGB port. mem_ready (a non-BRAM control register) keeps the
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// async reset for clean post-reset behavior. Same split as the legacy
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// chirp_memory_loader_param.v.
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// ============================================================================
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module chirp_reference_rom (
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input wire clk,
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input wire reset_n,
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input wire [1:0] wave_sel, // RP_WAVE_{SHORT,MEDIUM,LONG}
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input wire [1:0] segment_select, // [0]=LONG seg index; ignored for SHORT/MEDIUM
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input wire mem_request,
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input wire [10:0] sample_addr, // 0..2047 within the active waveform/segment
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output reg [15:0] ref_i,
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output reg [15:0] ref_q,
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output reg mem_ready
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);
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// -----------------------------------------------------------------------
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// BRAM arrays (one per Q15 lane). Vivado infers RAMB18 with sync read.
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// -----------------------------------------------------------------------
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(* ram_style = "block" *) reg [15:0] mem_i [0:8191];
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(* ram_style = "block" *) reg [15:0] mem_q [0:8191];
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// -----------------------------------------------------------------------
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// Initialization — load 4 distinct .mem files into 4 contiguous regions
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// of the unified BRAM. $readmemh range form lets us target each 2048-cell
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// segment independently. Vivado honors these for RAMB18 init contents.
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// -----------------------------------------------------------------------
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initial begin
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$readmemh("rx_short_i.mem", mem_i, 0, 2047);
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$readmemh("rx_short_q.mem", mem_q, 0, 2047);
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$readmemh("rx_medium_i.mem", mem_i, 2048, 4095);
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$readmemh("rx_medium_q.mem", mem_q, 2048, 4095);
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$readmemh("rx_long_seg0_i.mem", mem_i, 4096, 6143);
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$readmemh("rx_long_seg0_q.mem", mem_q, 4096, 6143);
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$readmemh("rx_long_seg1_i.mem", mem_i, 6144, 8191);
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$readmemh("rx_long_seg1_q.mem", mem_q, 6144, 8191);
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end
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// -----------------------------------------------------------------------
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// Address mux — combinational. Encodes the region select into addr[12:11]
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// and passes sample_addr through addr[10:0].
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// -----------------------------------------------------------------------
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reg [12:0] full_addr;
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always @(*) begin
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case (wave_sel)
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`RP_WAVE_SHORT: full_addr = {2'b00, sample_addr};
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`RP_WAVE_MEDIUM: full_addr = {2'b01, sample_addr};
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`RP_WAVE_LONG: full_addr = {1'b1, segment_select[0], sample_addr};
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default: full_addr = 13'd0; // RP_WAVE_RESERVED — read-zero region
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endcase
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end
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// -----------------------------------------------------------------------
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// BRAM read block — sync-only, sync reset (REQP-1839/1840). Single stage:
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// ref_i / ref_q valid 1 clk after mem_request, matching legacy timing.
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// -----------------------------------------------------------------------
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always @(posedge clk) begin
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if (!reset_n) begin
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ref_i <= 16'd0;
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ref_q <= 16'd0;
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end else if (mem_request) begin
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ref_i <= mem_i[full_addr];
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ref_q <= mem_q[full_addr];
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end
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end
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// -----------------------------------------------------------------------
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// Control register — async-resettable. mem_ready follows mem_request by
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// 1 clk to match the BRAM read latency.
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// -----------------------------------------------------------------------
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n)
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mem_ready <= 1'b0;
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else
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mem_ready <= mem_request;
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end
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endmodule
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