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PLFM_RADAR/9_Firmware/9_2_FPGA
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Jason 2401f5f89e fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19) 
CFAR pipeline fix (clk_100m WNS: -0.331ns → +0.156ns):
- Pre-register col_buf reads during ST_CFAR_THR pipeline stage
- 8 pipeline registers (4 values + 4 valids) break 15-level mux tree
- Delta wires use registered values, eliminating combinatorial depth

CIC reset path fix (clk_mmcm_out0 WNS: -0.074ns → +0.068ns):
- Add reset_h input port to cic_decimator_4x_enhanced.v
- Remove internal wire reset_h = ~reset_n (LUT1 inverter was root cause)
- Wire pre-registered reset_400m from ddc_400m.v into both CIC instances
- 3 sync reset blocks changed from if(!reset_n) to if(reset_h)

Build 19 results (xc7a50tftg256-2, Vivado 2025.2):
- All 5 clock domains timing met, 0 failing endpoints
- WNS: +0.068ns (400MHz), +0.156ns (100MHz), +0.627ns (120MHz)
- Utilization: 66.67% LUT, 22.36% FF, 74% BRAM, 93.33% DSP
- Bitstream: 2,140 KB
2026-04-16 23:09:31 +05:45
..
constraints
fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review
2026-04-14 00:08:26 +05:45
formal
fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)
2026-04-06 23:15:50 +03:00
scripts
feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix
2026-04-13 19:24:11 +05:45
tb
fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)
2026-04-16 23:09:31 +05:45
.gitignore
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
2026-03-19 11:31:46 +02:00
ad9484_interface_400m.v
fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-target bank voltage compatibility
2026-04-07 05:17:11 +03:00
adc_clk_mmcm_integration.md
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
adc_clk_mmcm.v
fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review
2026-04-14 00:08:26 +05:45
cdc_modules.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
cfar_ca.v
fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)
2026-04-16 23:09:31 +05:45
chirp_memory_loader_param.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
cic_decimator_4x_enhanced.v
fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)
2026-04-16 23:09:31 +05:45
dac_interface_single.v
Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I
2026-03-16 22:24:22 +02:00
ddc_400m.v
fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)
2026-04-16 23:09:31 +05:45
ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
doppler_processor.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
edge_detector.v
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
2026-03-17 13:48:47 +02:00
fft_engine.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
fft_twiddle_16.mem
Fix staggered-PRF Doppler processing with dual 16-point FFTs
2026-03-27 23:05:28 +02:00
fft_twiddle_1024.mem
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
fft_twiddle_2048.mem
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
fir_lowpass.v
fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butterfly on 50T
2026-04-07 14:45:47 +03:00
fpga_self_test.v
fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review
2026-04-14 00:08:26 +05:45
frequency_matched_filter.v
Convert async→sync reset on DSP/BRAM datapath registers for timing closure
2026-03-17 20:11:13 +02:00
latency_buffer.v
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00
long_chirp_lut.mem
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
long_chirp_seg0_i.mem
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
long_chirp_seg0_q.mem
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
long_chirp_seg1_i.mem
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
long_chirp_seg1_q.mem
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
matched_filter_multi_segment.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
matched_filter_processing_chain.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
mti_canceller.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
nco_400m_enhanced.v
Improve timing margins with targeted datapath register tuning
2026-03-17 23:51:04 +02:00
plfm_chirp_controller.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
radar_mode_controller.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
radar_params.vh
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
radar_receiver_final.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
radar_system_top_50t.v
feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix
2026-04-13 19:24:11 +05:45
radar_system_top_te0712_dev.v
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
radar_system_top_te0713_dev.v
Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments
2026-03-19 16:47:59 +02:00
radar_system_top_te0713_umft601x_dev.v
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
2026-03-21 20:43:52 +02:00
radar_system_top.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
radar_transmitter.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
range_bin_decimator.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
run_regression.sh
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
rx_gain_control.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
short_chirp_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
short_chirp_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
usb_data_interface_ft2232h.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
usb_data_interface.v
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
2026-04-16 17:27:55 +05:45
xfft_16.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00