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PLFM_RADAR/9_Firmware/9_2_FPGA/tb
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Jason 21bf7a0228 feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback 
Closes the 161-µs MEDIUM PRI visibility gap from the 2026-05-02 e2e audit.
PR-G ran out of reserved bits in status_words[3] to fit a second 16-bit
pair, so this PR adds status_words[7] = {medium_chirp[15:0], medium_listen[15:0]}
and bumps STATUS_PKT_LEN 30→34, STATUS_PACKET_SIZE 30→34.

RTL (usb_data_interface_ft2232h.v):
  - Two new input ports `status_medium_chirp` / `status_medium_listen`.
  - status_words array bound 6→7, init loop 7→8, snapshot block packs word 7.
  - STATUS_PKT_LEN width 5→6 bits to hold 34, byte-mux index widened
    [4:0]→[5:0] with 4 new entries for word 7 + footer at index 33.
  - Header docstring + length-localparam comment refreshed.

Top-level (radar_system_top.v): wire `host_medium_chirp_cycles` /
`host_medium_listen_cycles` into the FT2232H usb_inst (gen_ft2232h branch
only; legacy FT601 path retains its pre-PR-G 6-word / 26-byte layout —
no host code reads it today).

Host parser (radar_protocol.py):
  - STATUS_PACKET_SIZE 30→34. Module docstring + parse_status_packet
    docstring + find_bulk_frame_boundaries note refreshed.
  - StatusResponse gains `medium_chirp` / `medium_listen` fields.
  - Word-loop bounds 7→8; word-7 decode added.

Tests:
  - tb_usb_protocol_v2 — drive default RP_DEF_MEDIUM_*_CYCLES (500/15600),
    move T3.2 footer assertion 29→33, add T3.8..T3.11 for word-7 bytes.
    Manual run: 31/31 PASS (TB not in run_regression.sh).
  - tb_ft2232h_frame_drop, tb_e2e_dsp_to_host — tie new DUT ports to
    16'd0 (these TBs don't exercise status reads).
  - test_GUI_V65_Tk — extend _make_status_packet builder kwargs, rename
    test_status_packet_is_30_bytes → _is_34_bytes, add round-trip +
    16-bit-max tests for word 7.
  - test_v7 — TestStatusPacketV2RoundTrip rewired for 8 words / 34 B,
    add test_word7_medium_pri_decoded + test_pre_M5_30byte_packet_rejected.

Verification:
  - FPGA regression (iverilog + xsim cosim): 42/0/0.
  - tb_usb_protocol_v2 standalone: 31/0.
  - Host test_GUI_V65_Tk: 119/119.
  - Host test_v7: 152/152.
2026-05-07 15:20:09 +05:45
..
cosim
fix(fpga): PR-AA — doppler_mag 1-cell shift in usb emit FSM
2026-05-06 10:30:54 +05:45
golden
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
ad9484_interface_400m_stub.v
test(fpga): PR-X.1 F-7.4 — gate tb_ad9484_xsim on MMCM lock (closes PR-N #86)
2026-05-05 11:59:30 +05:45
cic_dc_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_impulse_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_sine_passband.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
ddc_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
fir_dc_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_impulse_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_sine_passband.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
gen_mf_golden_ref.py
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_summary.txt
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_pipeline_output.csv
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
nco_1mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_freq_switch.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_quadrature.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
tb_ad9484_xsim.v
docs(fpga): PR-X.2 F-7.3 — refresh tb_ad9484_xsim header + retire Group 4
2026-05-05 13:48:30 +05:45
tb_adc_pwdn_opcode.v
fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)
2026-04-29 19:37:37 +05:45
tb_audit_c16_num_cells.v
AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T
2026-04-29 23:01:41 +05:45
tb_cdc_async_fifo.v
AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO
2026-04-30 10:47:31 +05:45
tb_cdc_modules.v
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
tb_cfar_ca.v
chirp-v2 PR-F: doppler/CFAR widen to 3 sub-frames + 2-class detect
2026-05-01 03:36:03 +05:45
tb_chirp_contract.v
chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO
2026-04-30 21:51:46 +05:45
tb_chirp_controller.v
chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO
2026-04-30 21:51:46 +05:45
tb_cic_decimator.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ddc_400m.v
fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33
2026-04-29 14:18:25 +05:45
tb_ddc_cosim.v
fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33
2026-04-29 14:18:25 +05:45
tb_ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
tb_dig6_frame_pulse.v
feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy
2026-05-07 13:29:48 +05:45
tb_doppler_cosim.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_doppler_frame_start_gate.v
chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment
2026-05-01 04:35:08 +05:45
tb_doppler_realdata.v
test(realdata): PR-K — synthetic regen of doppler/fullchain realdata fixtures
2026-05-01 14:26:54 +05:45
tb_e2e_dsp_to_host.v
feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback
2026-05-07 15:20:09 +05:45
tb_edge_detector.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_fft_engine_axi_bridge.v
fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O
2026-05-02 10:08:00 +05:45
tb_fft_engine.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_fir_lowpass.v
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
tb_fpga_self_test.v
AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic
2026-04-29 23:27:15 +05:45
tb_freq_matched_filter.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ft2232h_frame_drop.v
feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback
2026-05-07 15:20:09 +05:45
tb_fullchain_realdata.v
test(realdata): PR-K — synthetic regen of doppler/fullchain realdata fixtures
2026-05-01 14:26:54 +05:45
tb_matched_filter_processing_chain.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_mf_cosim.v
cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain
2026-04-27 14:06:55 +05:45
tb_mf_long_chirp.v
fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)
2026-05-01 15:07:19 +05:45
tb_mti_canceller.v
chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native
2026-04-30 20:52:32 +05:45
tb_multiseg_cosim.v
chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native
2026-04-30 20:52:32 +05:45
tb_nco_400m.v
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
tb_nco_xsim.v
Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization
2026-03-16 23:23:06 +02:00
tb_radar_receiver_final.v
fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)
2026-05-02 13:37:06 +05:45
tb_range_bin_decimator.v
merge(wave3/tier2): port testbenches and cosim goldens for fft-2048
2026-04-21 03:04:52 +05:45
tb_rx_gain_control.v
fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes
2026-04-13 23:35:10 +05:45
tb_rxb_fullchain_latency.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_rxb_latency_measure.v
cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain
2026-04-27 14:06:55 +05:45
tb_status_words_stickies.v
feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy
2026-05-07 13:29:48 +05:45
tb_system_mechanics.v
fix(fpga): PR-Z A6 — usb cfar dense bug end-to-end fix + e2e test
2026-05-06 01:20:19 +05:45
tb_system_opcodes.v
test(opcodes): PR-I.1 — tb_system_opcodes via production FT2232H path
2026-05-01 12:07:31 +05:45
tb_threshold_detector.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
tb_usb_data_interface.v
AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T
2026-04-29 23:01:41 +05:45
tb_usb_protocol_v2.v
feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback
2026-05-07 15:20:09 +05:45
tb_xfft_2048_xsim.v
fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O
2026-05-02 10:08:00 +05:45