ada170ef1f
FPGA (Phase 1+2): - gpio_dig6 (PD14) now carries chirp_scheduler frame_pulse, FPGA-stretched to ~100 ns so the STM32 EXTI on PD14 can latch reliably. - gpio_dig7 (PD15) returns to its pre-PR-AB.b role: control-fault OR (range_decim_watchdog | CDC overrun); MCU stuck-high sampler unchanged. - rx_range_decim_watchdog gains a sticky in source clock domain so a slow status poll cannot miss a 1-cycle assertion (Phase 1). - New tb_dig6_frame_pulse.v (13 checks); tb_status_words_stickies.v extended with DIG_7 fault-OR coverage (14 checks); retired tb_audit_s10_gpio_split.v. - Port comments in radar_system_top.v / _50t.v and XDC roles refreshed. MCU (Phase 3): - PD14 reconfigured to GPIO_MODE_IT_RISING + GPIO_PULLDOWN; new EXTI15_10_IRQHandler in stm32f7xx_it.c dispatches to HAL_GPIO_EXTI_Callback that bumps a volatile g_frame_pulse_count. - runRadarPulseSequence dwell loop replaces 3x HAL_Delay(8) with waitForFramePulse(20) — per-pattern dwell now tracks the actual mask-aware ladder length (drift-free, mask-aware), with a 20 ms timeout safety net. - AGC outer loop is ALWAYS-ON in production (compile-time policy); bench builds compile the body out via -DMCU_AGC_FORCE_DISABLED. The runtime enable/debounce + DIG_6 polling that previously gated AGC are removed. - main.h adds FPGA_FRAME_PULSE_* aliases pointing at FPGA_DIG6_*. GUI (Phase 4): - Settings tab gains a Bench / Diagnostics group with a BENCH-MODE checkbox (off by default, persisted via QSettings). - AGC group header swaps between a green "AGC: ALWAYS-ON" badge (production) and Enable/Disable AGC buttons (bench), pinned to the top of the group. The redundant 0/1 spinbox row for opcode 0x28 is removed — buttons send the same opcode and cannot accept invalid input. - Both the FPGA Control AGC Status box and the AGC Monitor strip share a helper that honours bench-mode in production (always shows ALWAYS-ON in green so the two views never disagree with the badge). - _add_fpga_param_row uses setFixedWidth on label and Set button + explicit stretch=1 on the hint, so all rows align column-wise whether they sit directly in a QVBoxLayout or inside a wrapper QWidget. Regression: FPGA 42/0/0 (PR-M.4 baseline) - MCU 34/34 - GPS extended 51/51 - GUI v7 150/150 - BENCH-MODE flip behaviorally verified. Hardware-blocked steps deferred: bench-scope verify (PD14 dwell pulse, counter advance, PD15 stuck-high recovery still triggers). Closes #182.
541 lines
30 KiB
Tcl
541 lines
30 KiB
Tcl
# ============================================================================
|
||
# RADAR SYSTEM FPGA CONSTRAINTS
|
||
# ============================================================================
|
||
# Device: XC7A50T-2FTG256I (FTG256 package)
|
||
# Board: AERIS-10 Phased Array Radar — Main Board
|
||
# Source: Pin assignments extracted from Eagle schematic (RADAR_Main_Board.sch)
|
||
# FPGA = U42
|
||
#
|
||
# NOTE: The README and prior version of this file incorrectly referenced
|
||
# XC7A100TCSG324-1. The physical board uses XC7A50T in a 256-ball BGA
|
||
# (FTG256). All PACKAGE_PIN values below are FTG256 ball locations.
|
||
#
|
||
# I/O Bank Voltage Summary:
|
||
# Bank 0: VCCO = 3.3V (JTAG, flash CS)
|
||
# Bank 14: VCCO = 2.5V (ADC LVDS_25 data — placer-enforced; adc_pwdn as LVCMOS25)
|
||
# Bank 15: VCCO = 3.3V (DAC, clocks, STM32 SPI 3.3V side, DIG bus, mixer)
|
||
# Bank 34: VCCO = 1.8V (ADAR1000 beamformer control, SPI 1.8V side)
|
||
# Bank 35: VCCO = 3.3V (FT2232H USB 2.0 FIFO — 15 signals)
|
||
#
|
||
# DRC Fix History:
|
||
# - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC).
|
||
# Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair.
|
||
# - BIVC-1 / Place 30-372: Bank 14 must have a single VCCO. LVDS_25 forces
|
||
# VCCO=2.5V, so adc_pwdn was changed from LVCMOS33 to LVCMOS25 to match.
|
||
# IBUFDS input buffers are VCCO-independent. BIVC-1 also waived via
|
||
# set_property SEVERITY in the build script as an additional safety net.
|
||
# in the build script. adc_pwdn (LVCMOS25) coexists in the same bank.
|
||
# - UCIO/NSTD: Unconstrained ports (FT601 ports inactive with USB_MODE=1,
|
||
# status/debug outputs have no physical pins). Handled with SEVERITY
|
||
# demotion + default IOSTANDARD.
|
||
# - PLIO-9: FT2232H CLKOUT routed to C4 (IO_L12N_T1_MRCC_35, N-type).
|
||
# Clock inputs normally use P-type MRCC pins, but IBUFG works correctly
|
||
# on N-type. Demote PLIO-9 to warning in build script.
|
||
# ============================================================================
|
||
|
||
# ============================================================================
|
||
# CONFIGURATION
|
||
# ============================================================================
|
||
set_property CFGBVS VCCO [current_design]
|
||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||
|
||
# ============================================================================
|
||
# DRC WAIVERS — Hardware-Level Known Issues (applied in build script)
|
||
# ============================================================================
|
||
# BIVC-1: Bank 14 VCCO=3.3V with LVDS_25 inputs + LVCMOS33 adc_pwdn.
|
||
# IBUFDS input buffers are VCCO-independent on 7-series — they use an
|
||
# internal differential amplifier that works correctly at any VCCO.
|
||
# The BIVC-1 DRC check is intended for OBUFDS *outputs* where VCCO
|
||
# directly affects the output swing. Since Bank 14 has only LVDS inputs
|
||
# and one LVCMOS33 output, this is safe to demote to a warning.
|
||
# → Applied in build_50t_test.tcl: set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
|
||
#
|
||
# NSTD-1 / UCIO-1: Unconstrained ports — FT601 USB ports (inactive with
|
||
# USB_MODE=1 generate block), dac_clk (DAC clock comes from AD9523, not FPGA),
|
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# and all status/debug outputs (no physical pins available). These ports are
|
||
# present in the shared RTL but have no connections on the 50T board.
|
||
# → Applied in build_50t_test.tcl: set_property SEVERITY {Warning} [get_drc_checks {NSTD-1 UCIO-1}]
|
||
|
||
# ============================================================================
|
||
# CLOCK CONSTRAINTS
|
||
# ============================================================================
|
||
|
||
# 100MHz System Clock (AD9523 OUT6 → FPGA_SYS_CLOCK → Bank 15 MRCC pin E12)
|
||
set_property PACKAGE_PIN E12 [get_ports {clk_100m}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {clk_100m}]
|
||
create_clock -name clk_100m -period 10.0 [get_ports {clk_100m}]
|
||
set_input_jitter [get_clocks clk_100m] 0.1
|
||
|
||
# 120MHz DAC Clock (AD9523 OUT11 → FPGA_DAC_CLOCK → Bank 15 MRCC pin D13)
|
||
# NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
|
||
# AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
|
||
# uses this clock input for internal DAC data timing only. The RTL port
|
||
# `dac_clk` is an RTL output that assigns clk_120m directly. It has no
|
||
# physical pin on the 50T board and is left unconnected here. The port
|
||
# CANNOT be removed from the RTL because the 200T board uses it with
|
||
# ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
|
||
# FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
|
||
# Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
|
||
set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {clk_120m_dac}]
|
||
create_clock -name clk_120m_dac -period 8.333 [get_ports {clk_120m_dac}]
|
||
set_input_jitter [get_clocks clk_120m_dac] 0.1
|
||
|
||
# ADC DCO Clock (400MHz LVDS — AD9523 OUT5 → AD9484 → FPGA, Bank 14 MRCC)
|
||
# NOTE: LVDS_25 is the only valid differential input standard on 7-series HR
|
||
# banks. IBUFDS input buffers are VCCO-independent — they work correctly even
|
||
# with VCCO=3.3V. The BIVC-1 DRC (voltage conflict with LVCMOS33 adc_pwdn)
|
||
# is waived in the build script since this bank has only LVDS *inputs*.
|
||
set_property PACKAGE_PIN N14 [get_ports {adc_dco_p}]
|
||
set_property PACKAGE_PIN P14 [get_ports {adc_dco_n}]
|
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set_property IOSTANDARD LVDS_25 [get_ports {adc_dco_p}]
|
||
set_property IOSTANDARD LVDS_25 [get_ports {adc_dco_n}]
|
||
set_property DIFF_TERM TRUE [get_ports {adc_dco_p}]
|
||
create_clock -name adc_dco_p -period 2.5 [get_ports {adc_dco_p}]
|
||
set_input_jitter [get_clocks adc_dco_p] 0.05
|
||
|
||
# --------------------------------------------------------------------------
|
||
# FT2232H 60 MHz CLKOUT (Bank 35, MRCC pin C4)
|
||
# --------------------------------------------------------------------------
|
||
# The FT2232H provides a 60 MHz clock in 245 Synchronous FIFO mode.
|
||
# Pin C4 is IO_L12N_T1_MRCC_35 (N-type of MRCC pair). Vivado requires
|
||
# CLOCK_DEDICATED_ROUTE FALSE for clock inputs on N-type MRCC pins
|
||
# (Place 30-876). The schematic routes CLKOUT to C4; this cannot be
|
||
# changed without a board respin. The clock still uses an IBUFG and
|
||
# reaches the clock network — the constraint only disables the DRC check.
|
||
set_property PACKAGE_PIN C4 [get_ports {ft_clkout}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_clkout}]
|
||
create_clock -name ft_clkout -period 16.667 [get_ports {ft_clkout}]
|
||
set_input_jitter [get_clocks ft_clkout] 0.2
|
||
# N-type MRCC pin requires dedicated route override (Place 30-876).
|
||
# Audit F-0.4: the literal net name `ft_clkout_IBUF` exists post-synth but
|
||
# the XDC scan happens before synthesis, when the IBUF net does not yet
|
||
# exist — Vivado reported `No nets matched 'ft_clkout_IBUF'` + CRITICAL
|
||
# WARNING. Use -hierarchical -filter + -quiet so the constraint matches
|
||
# post-synth without warning during pre-synth XDC scan. The TCL duplicate
|
||
# at scripts/50t/build_50t.tcl:119 remains as belt-and-suspenders.
|
||
set_property -quiet CLOCK_DEDICATED_ROUTE FALSE \
|
||
[get_nets -quiet -hierarchical -filter {NAME =~ *ft_clkout_IBUF}]
|
||
|
||
# ============================================================================
|
||
# RESET (Active-Low)
|
||
# ============================================================================
|
||
# DIG_4 (STM32 PD12 → FPGA Bank 15 pin E15)
|
||
# STM32 firmware uses HAL_GPIO_WritePin to assert/deassert FPGA reset.
|
||
|
||
set_property PACKAGE_PIN E15 [get_ports {reset_n}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {reset_n}]
|
||
set_property PULLUP true [get_ports {reset_n}]
|
||
|
||
# ============================================================================
|
||
# TRANSMITTER INTERFACE (DAC — Bank 15, VCCO=3.3V)
|
||
# ============================================================================
|
||
|
||
# DAC Data Bus (8-bit) — AD9708 data inputs via schematic nets DAC_0..DAC_7
|
||
set_property PACKAGE_PIN A14 [get_ports {dac_data[0]}]
|
||
set_property PACKAGE_PIN A13 [get_ports {dac_data[1]}]
|
||
set_property PACKAGE_PIN A12 [get_ports {dac_data[2]}]
|
||
set_property PACKAGE_PIN B11 [get_ports {dac_data[3]}]
|
||
set_property PACKAGE_PIN B10 [get_ports {dac_data[4]}]
|
||
set_property PACKAGE_PIN A10 [get_ports {dac_data[5]}]
|
||
set_property PACKAGE_PIN A9 [get_ports {dac_data[6]}]
|
||
set_property PACKAGE_PIN A8 [get_ports {dac_data[7]}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {dac_data[*]}]
|
||
set_property SLEW FAST [get_ports {dac_data[*]}]
|
||
set_property DRIVE 8 [get_ports {dac_data[*]}]
|
||
|
||
# DAC Clock Output — NOT DIRECTLY WIRED TO DAC IN SCHEMATIC
|
||
# The DAC chip (U3) receives its clock from AD9523 via a separate net
|
||
# (DAC_CLOCK), not from the FPGA. The RTL `dac_clk` output has no
|
||
# physical pin. Comment out or remove from RTL.
|
||
# set_property PACKAGE_PIN ??? [get_ports {dac_clk}]
|
||
# set_property IOSTANDARD LVCMOS33 [get_ports {dac_clk}]
|
||
# set_property SLEW FAST [get_ports {dac_clk}]
|
||
|
||
# DAC Sleep Control — DAC_SLEEP net
|
||
set_property PACKAGE_PIN A15 [get_ports {dac_sleep}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {dac_sleep}]
|
||
|
||
# RF Switch Control — M3S_VCTRL net
|
||
set_property PACKAGE_PIN G15 [get_ports {fpga_rf_switch}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {fpga_rf_switch}]
|
||
|
||
# Mixer Enables — MIX_RX_EN, MIX_TX_EN nets
|
||
set_property PACKAGE_PIN D11 [get_ports {rx_mixer_en}]
|
||
set_property PACKAGE_PIN C11 [get_ports {tx_mixer_en}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {rx_mixer_en}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {tx_mixer_en}]
|
||
|
||
# ============================================================================
|
||
# ADAR1000 BEAMFORMER CONTROL (Bank 34, VCCO=1.8V)
|
||
# ============================================================================
|
||
|
||
# ADAR1000 TX Load Pins (via level shifters, active-high pulse)
|
||
set_property PACKAGE_PIN P3 [get_ports {adar_tx_load_1}]
|
||
set_property PACKAGE_PIN T4 [get_ports {adar_tx_load_2}]
|
||
set_property PACKAGE_PIN R3 [get_ports {adar_tx_load_3}]
|
||
set_property PACKAGE_PIN R2 [get_ports {adar_tx_load_4}]
|
||
|
||
# ADAR1000 RX Load Pins
|
||
set_property PACKAGE_PIN M5 [get_ports {adar_rx_load_1}]
|
||
set_property PACKAGE_PIN T2 [get_ports {adar_rx_load_2}]
|
||
set_property PACKAGE_PIN R1 [get_ports {adar_rx_load_3}]
|
||
set_property PACKAGE_PIN N4 [get_ports {adar_rx_load_4}]
|
||
|
||
# Bank 34 VCCO = 1.8V → must use LVCMOS18 (not LVCMOS33)
|
||
set_property IOSTANDARD LVCMOS18 [get_ports {adar_*_load_*}]
|
||
|
||
# ADAR1000 TR (Transmit/Receive) Pins
|
||
set_property PACKAGE_PIN N2 [get_ports {adar_tr_1}]
|
||
set_property PACKAGE_PIN N1 [get_ports {adar_tr_2}]
|
||
set_property PACKAGE_PIN P1 [get_ports {adar_tr_3}]
|
||
set_property PACKAGE_PIN P4 [get_ports {adar_tr_4}]
|
||
set_property IOSTANDARD LVCMOS18 [get_ports {adar_tr_*}]
|
||
|
||
# ============================================================================
|
||
# LEVEL SHIFTER SPI INTERFACE (STM32 ↔ ADAR1000)
|
||
# ============================================================================
|
||
|
||
# 3.3V Side (from STM32, Bank 15, VCCO=3.3V)
|
||
set_property PACKAGE_PIN J16 [get_ports {stm32_sclk_3v3}]
|
||
set_property PACKAGE_PIN H13 [get_ports {stm32_mosi_3v3}]
|
||
set_property PACKAGE_PIN G14 [get_ports {stm32_miso_3v3}]
|
||
set_property PACKAGE_PIN F14 [get_ports {stm32_cs_adar1_3v3}]
|
||
set_property PACKAGE_PIN H16 [get_ports {stm32_cs_adar2_3v3}]
|
||
set_property PACKAGE_PIN G16 [get_ports {stm32_cs_adar3_3v3}]
|
||
set_property PACKAGE_PIN J15 [get_ports {stm32_cs_adar4_3v3}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {stm32_*_3v3}]
|
||
|
||
# 1.8V Side (to ADAR1000, Bank 34, VCCO=1.8V)
|
||
set_property PACKAGE_PIN P5 [get_ports {stm32_sclk_1v8}]
|
||
set_property PACKAGE_PIN M1 [get_ports {stm32_mosi_1v8}]
|
||
set_property PACKAGE_PIN N3 [get_ports {stm32_miso_1v8}]
|
||
set_property PACKAGE_PIN L5 [get_ports {stm32_cs_adar1_1v8}]
|
||
set_property PACKAGE_PIN L4 [get_ports {stm32_cs_adar2_1v8}]
|
||
set_property PACKAGE_PIN M4 [get_ports {stm32_cs_adar3_1v8}]
|
||
set_property PACKAGE_PIN M2 [get_ports {stm32_cs_adar4_1v8}]
|
||
set_property IOSTANDARD LVCMOS18 [get_ports {stm32_*_1v8}]
|
||
|
||
# ============================================================================
|
||
# STM32 CONTROL INTERFACE (DIG bus, Bank 15, VCCO=3.3V)
|
||
# ============================================================================
|
||
# DIG_0..DIG_4 are STM32 outputs (PD8-PD12) → FPGA inputs (control)
|
||
# DIG_5..DIG_7 are STM32 inputs (PD13-PD15) ← FPGA outputs (status / sync)
|
||
|
||
set_property PACKAGE_PIN F13 [get_ports {stm32_new_chirp}] ;# DIG_0 (PD8)
|
||
set_property PACKAGE_PIN E16 [get_ports {stm32_new_elevation}] ;# DIG_1 (PD9)
|
||
set_property PACKAGE_PIN D16 [get_ports {stm32_new_azimuth}] ;# DIG_2 (PD10)
|
||
set_property PACKAGE_PIN F15 [get_ports {stm32_mixers_enable}] ;# DIG_3 (PD11)
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
|
||
# reset_n is DIG_4 (PD12) — constrained above in the RESET section
|
||
|
||
# DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — FPGA→STM32 status / sync outputs
|
||
# DIG_5 (PD13): signal-chain saturation flag — drives MCU outer-loop AGC.
|
||
# DIG_6 (PD14): stretched chirp_scheduler frame_pulse (~100 ns) — PR-AB.b
|
||
# STM32 EXTI rising edge for drift-free dwell sync.
|
||
# DIG_7 (PD15): control-chain fault OR — F-6.4 range_decim_watchdog
|
||
# | F-1.2 CIC→FIR CDC overrun. MCU PD15 stuck-high sampler
|
||
# triggers attemptErrorRecovery(ERROR_FPGA_DSP_STALL).
|
||
set_property PACKAGE_PIN H11 [get_ports {gpio_dig5}]
|
||
set_property PACKAGE_PIN G12 [get_ports {gpio_dig6}]
|
||
set_property PACKAGE_PIN H12 [get_ports {gpio_dig7}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_dig*}]
|
||
set_property DRIVE 8 [get_ports {gpio_dig*}]
|
||
set_property SLEW SLOW [get_ports {gpio_dig*}]
|
||
|
||
# ============================================================================
|
||
# ADC INTERFACE (LVDS — Bank 14, VCCO=3.3V)
|
||
# ============================================================================
|
||
|
||
# ADC Data (8-bit LVDS pairs from AD9484)
|
||
set_property PACKAGE_PIN P15 [get_ports {adc_d_p[0]}]
|
||
set_property PACKAGE_PIN P16 [get_ports {adc_d_n[0]}]
|
||
set_property PACKAGE_PIN R15 [get_ports {adc_d_p[1]}]
|
||
set_property PACKAGE_PIN R16 [get_ports {adc_d_n[1]}]
|
||
set_property PACKAGE_PIN T14 [get_ports {adc_d_p[2]}]
|
||
set_property PACKAGE_PIN T15 [get_ports {adc_d_n[2]}]
|
||
set_property PACKAGE_PIN R13 [get_ports {adc_d_p[3]}]
|
||
set_property PACKAGE_PIN T13 [get_ports {adc_d_n[3]}]
|
||
set_property PACKAGE_PIN R10 [get_ports {adc_d_p[4]}]
|
||
set_property PACKAGE_PIN R11 [get_ports {adc_d_n[4]}]
|
||
set_property PACKAGE_PIN T9 [get_ports {adc_d_p[5]}]
|
||
set_property PACKAGE_PIN T10 [get_ports {adc_d_n[5]}]
|
||
set_property PACKAGE_PIN T7 [get_ports {adc_d_p[6]}]
|
||
set_property PACKAGE_PIN T8 [get_ports {adc_d_n[6]}]
|
||
set_property PACKAGE_PIN R6 [get_ports {adc_d_p[7]}]
|
||
set_property PACKAGE_PIN R7 [get_ports {adc_d_n[7]}]
|
||
|
||
# ADC DCO Clock (LVDS) — already constrained above in CLOCK section
|
||
|
||
# ADC Power Down — ADC_PWRD net (single-ended, Bank 14)
|
||
# Uses LVCMOS25 to be voltage-compatible with LVDS_25 in the same bank.
|
||
# The placer enforces a single VCCO per bank; LVDS_25 demands VCCO=2.5V.
|
||
# LVCMOS25 output drives the AD9484 PWDN pin (CMOS threshold ~0.8V) safely.
|
||
# On the physical board (VCCO=3.3V), output swings follow actual VCCO.
|
||
set_property PACKAGE_PIN T5 [get_ports {adc_pwdn}]
|
||
set_property IOSTANDARD LVCMOS25 [get_ports {adc_pwdn}]
|
||
|
||
# LVDS I/O Standard — LVDS_25 is the only valid differential input standard
|
||
# on 7-series HR banks. IBUFDS inputs work correctly regardless of VCCO.
|
||
set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}]
|
||
set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
|
||
|
||
# Differential termination — DIFF_TERM uses a ~100-ohm on-die termination
|
||
# inside the IBUFDS. This is VCCO-independent for 7-series input buffers.
|
||
# RTL IBUFDS uses DIFF_TERM("FALSE") so this XDC property takes precedence.
|
||
set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
|
||
|
||
# Input delay for ADC data relative to DCO (adjust based on PCB trace length)
|
||
# DDR interface: constrain both rising and falling clock edges
|
||
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_d_p[*]}]
|
||
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
|
||
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
|
||
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
|
||
|
||
# --------------------------------------------------------------------------
|
||
# Audit F-0.1: AD9484 OR (overrange) LVDS pair (Bank 14)
|
||
# Schematic RADAR_Main_Board.sch: ADC_OR_P → U42 IO_L19P_T3_A10_D26_14 (M6)
|
||
# ADC_OR_N → U42 IO_L19N_T3_A09_D25_VREF_14 (N6)
|
||
# DDR-sourced by adc_dco_p, same timing class as adc_d_p[*].
|
||
# --------------------------------------------------------------------------
|
||
set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
|
||
set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
|
||
set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
|
||
set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
|
||
set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
|
||
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_or_p}]
|
||
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_or_p}]
|
||
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_or_p}] -add_delay
|
||
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_or_p}] -add_delay
|
||
|
||
# ============================================================================
|
||
# FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
|
||
# ============================================================================
|
||
# FT2232H (U6) Channel A in 245 Synchronous FIFO mode.
|
||
# All signals are direct connections to FPGA Bank 35 (LVCMOS33).
|
||
# Pin mapping extracted from Eagle schematic (RADAR_Main_Board.sch).
|
||
#
|
||
# The FT2232H replaces the previously-unwired FT601 on the 50T production
|
||
# board. The 200T dev board retains FT601 USB 3.0 (32-bit).
|
||
# ============================================================================
|
||
|
||
# 8-bit bidirectional data bus (ADBUS0–ADBUS7)
|
||
set_property PACKAGE_PIN K1 [get_ports {ft_data[0]}] ;# ADBUS0 → IO_L22P_T3_35
|
||
set_property PACKAGE_PIN J3 [get_ports {ft_data[1]}] ;# ADBUS1 → IO_L21P_T3_DQS_35
|
||
set_property PACKAGE_PIN H3 [get_ports {ft_data[2]}] ;# ADBUS2 → IO_L21N_T3_DQS_35
|
||
set_property PACKAGE_PIN G4 [get_ports {ft_data[3]}] ;# ADBUS3 → IO_L16N_T2_35
|
||
set_property PACKAGE_PIN F2 [get_ports {ft_data[4]}] ;# ADBUS4 → IO_L15P_T2_DQS_35
|
||
set_property PACKAGE_PIN D1 [get_ports {ft_data[5]}] ;# ADBUS5 → IO_L10N_T1_AD15N_35
|
||
set_property PACKAGE_PIN C3 [get_ports {ft_data[6]}] ;# ADBUS6 → IO_L7P_T1_AD6P_35
|
||
set_property PACKAGE_PIN C1 [get_ports {ft_data[7]}] ;# ADBUS7 → IO_L9P_T1_DQS_AD7P_35
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_data[*]}]
|
||
|
||
# Control signals (active low where noted)
|
||
set_property PACKAGE_PIN A2 [get_ports {ft_rxf_n}] ;# ACBUS0 → IO_L8N_T1_AD14N_35
|
||
set_property PACKAGE_PIN B2 [get_ports {ft_txe_n}] ;# ACBUS1 → IO_L8P_T1_AD14P_35
|
||
set_property PACKAGE_PIN A3 [get_ports {ft_rd_n}] ;# ACBUS2 → IO_L4N_T0_35
|
||
set_property PACKAGE_PIN A4 [get_ports {ft_wr_n}] ;# ACBUS3 → IO_L3N_T0_DQS_AD5N_35
|
||
set_property PACKAGE_PIN A5 [get_ports {ft_siwu}] ;# ACBUS4 → IO_L3P_T0_DQS_AD5P_35
|
||
set_property PACKAGE_PIN B7 [get_ports {ft_oe_n}] ;# ACBUS6 → IO_L1P_T0_AD4P_35
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_rxf_n}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_txe_n}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_rd_n}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_wr_n}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_siwu}]
|
||
set_property IOSTANDARD LVCMOS33 [get_ports {ft_oe_n}]
|
||
|
||
# Output timing: SLEW FAST + DRIVE 8 for FT2232H signals
|
||
set_property SLEW FAST [get_ports {ft_rd_n}]
|
||
set_property SLEW FAST [get_ports {ft_wr_n}]
|
||
set_property SLEW FAST [get_ports {ft_oe_n}]
|
||
set_property SLEW FAST [get_ports {ft_siwu}]
|
||
set_property SLEW FAST [get_ports {ft_data[*]}]
|
||
set_property DRIVE 8 [get_ports {ft_rd_n}]
|
||
set_property DRIVE 8 [get_ports {ft_wr_n}]
|
||
set_property DRIVE 8 [get_ports {ft_oe_n}]
|
||
set_property DRIVE 8 [get_ports {ft_siwu}]
|
||
set_property DRIVE 8 [get_ports {ft_data[*]}]
|
||
|
||
# ft_clkout constrained above in CLOCK CONSTRAINTS section (C4, 60 MHz)
|
||
|
||
# --------------------------------------------------------------------------
|
||
# FT2232H Source-Synchronous Timing Constraints
|
||
# --------------------------------------------------------------------------
|
||
# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns).
|
||
# Values per FTDI TN_167 "FT2232H Synchronous FIFO Bus Bridge" — verify
|
||
# against the exact app-note revision before shipping.
|
||
#
|
||
# FPGA Read Path (FT2232H drives data/RXF#/TXE#, FPGA samples on CLKOUT↑):
|
||
# - t_co (CLKOUT↑ → data valid) max = 10.0 ns
|
||
# - t_coh (CLKOUT↑ → data hold) min = 0.5 ns
|
||
# - set_input_delay -max = t_co, -min = t_coh
|
||
#
|
||
# FPGA Write Path (FPGA drives data/WR#/RD#/OE#, FT2232H samples on CLKOUT↑):
|
||
# - t_su (data setup before CLKOUT↑) min = 3.5 ns (NOT 5 ns — prior
|
||
# constraint used a synthetic period-based back-calculation)
|
||
# - t_h (data hold after CLKOUT↑) min = 1.0 ns (NOT 0 — a 0 ns hold
|
||
# constraint produced no hold check at all)
|
||
# - set_output_delay -max = t_su, -min = -t_h (Vivado convention)
|
||
#
|
||
# Audit F-2026-04-20 Option B: the previous output_delay = 11.667 ns
|
||
# (= period − 5) over-constrained launch by ~8 ns vs the actual datasheet
|
||
# figure. Relaxing to 3.5 ns matches the chip's real setup requirement.
|
||
# --------------------------------------------------------------------------
|
||
|
||
# Input delays: FT2232H → FPGA (data bus and status signals)
|
||
set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_data[*]}]
|
||
set_input_delay -clock [get_clocks ft_clkout] -min 0.5 [get_ports {ft_data[*]}]
|
||
set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_rxf_n}]
|
||
set_input_delay -clock [get_clocks ft_clkout] -min 0.5 [get_ports {ft_rxf_n}]
|
||
set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_txe_n}]
|
||
set_input_delay -clock [get_clocks ft_clkout] -min 0.5 [get_ports {ft_txe_n}]
|
||
|
||
# Output delays: FPGA → FT2232H (control strobes and data bus when writing)
|
||
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_data[*]}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_data[*]}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_rd_n}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_rd_n}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_wr_n}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_wr_n}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_oe_n}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_oe_n}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_siwu}]
|
||
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_siwu}]
|
||
|
||
# ============================================================================
|
||
# STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
|
||
# ============================================================================
|
||
# The following RTL output ports have no corresponding FPGA pins in the
|
||
# schematic. The only FPGA→STM32 outputs available are DIG_5 (H11),
|
||
# DIG_6 (G12), and DIG_7 (H12) — only 3 pins for potentially 60+ signals.
|
||
#
|
||
# These constraints are commented out. If status readback is needed, either:
|
||
# (a) Multiplex selected status bits onto DIG_5/6/7, or
|
||
# (b) Send status data over the SPI interface, or
|
||
# (c) Route through USB once FT601 is wired.
|
||
#
|
||
# Ports affected:
|
||
# current_elevation[5:0], current_azimuth[5:0], current_chirp[5:0],
|
||
# new_chirp_frame, dbg_doppler_data[31:0], dbg_doppler_valid,
|
||
# dbg_doppler_bin[4:0], dbg_range_bin[5:0], system_status[3:0]
|
||
# ============================================================================
|
||
|
||
# ============================================================================
|
||
# TIMING EXCEPTIONS
|
||
# ============================================================================
|
||
|
||
# False paths for asynchronous STM32 control signals (active-edge toggle interface)
|
||
set_false_path -from [get_ports {stm32_new_*}]
|
||
set_false_path -from [get_ports {stm32_mixers_enable}]
|
||
|
||
# --------------------------------------------------------------------------
|
||
# Async reset recovery/removal false paths
|
||
#
|
||
# The async reset (reset_n) is held asserted for multiple clock cycles during
|
||
# power-on and system reset. The recovery/removal timing checks on CLR pins
|
||
# are over-constrained for this use case:
|
||
# - reset_sync_reg[1] fans out to 1000+ registers across the FPGA
|
||
# - Route delay alone exceeds the clock period (18+ ns for 10ns period)
|
||
# - Reset deassertion order is not functionally critical — all registers
|
||
# come out of reset within a few cycles of each other
|
||
# --------------------------------------------------------------------------
|
||
# Audit F-0.5: the literal cell name `reset_sync_reg[*]` does not match any
|
||
# cell in the post-synth netlist. The actual sync regs are
|
||
# `u_core/reset_sync_reg[0..1]`, `u_core/rx_inst/ddc/reset_sync_400m_reg[*]`,
|
||
# `u_core/gen_ft2232h.usb_inst/ft_reset_sync_reg[*]`, and peers under
|
||
# `u_core/reset_sync_120m_reg[*]`, `u_core/reset_sync_ft601_reg[*]`,
|
||
# `u_core/rx_inst/adc/reset_sync_400m_reg[*]`. The waiver below covers all
|
||
# of them by matching any register whose name contains `reset_sync`.
|
||
# Without this, STA runs recovery/removal on the fanout of each sync-chain
|
||
# output register (up to ~1000 loads pre-PR#113 replication).
|
||
set_false_path -from [get_cells -hierarchical -filter {NAME =~ *reset_sync*_reg*}] \
|
||
-to [get_pins -hierarchical -filter {REF_PIN_NAME == CLR || REF_PIN_NAME == PRE}]
|
||
|
||
# --------------------------------------------------------------------------
|
||
# Clock Domain Crossing false paths
|
||
# --------------------------------------------------------------------------
|
||
|
||
# clk_100m ↔ adc_dco_p (400 MHz): DDC has internal CDC synchronizers
|
||
set_false_path -from [get_clocks clk_100m] -to [get_clocks adc_dco_p]
|
||
set_false_path -from [get_clocks adc_dco_p] -to [get_clocks clk_100m]
|
||
|
||
# --------------------------------------------------------------------------
|
||
# CIC comb stages — multicycle path (4-cycle setup / 3-cycle hold)
|
||
# --------------------------------------------------------------------------
|
||
# Comb registers (cic_*/comb_reg[*], cic_*/comb_delay_reg[*][*],
|
||
# cic_*/comb_0_c_reg, cic_*/comb_0_ab_reg, cic_*/comb_0_p_reg) are clocked at
|
||
# adc_dco_p (400 MHz) but their CE pins are driven by data_valid_comb_pipe /
|
||
# data_valid_comb_0_out, which fire once every 4 cycles after the 4× decimator.
|
||
# Effective throughput is 100 MHz, so STA can budget 4·2.5 ns = 10 ns of setup
|
||
# slack instead of 2.5 ns. This frees the DSP48E1s these stages previously
|
||
# occupied (5 per channel × 2 channels = 10 DSPs) and lets fabric carry-chain
|
||
# subtracts close timing comfortably. See cic_decimator_4x_enhanced.v header
|
||
# comment on the comb array declaration.
|
||
set_multicycle_path 4 -setup \
|
||
-from [get_cells -hierarchical -filter {NAME =~ *cic_*/comb_*reg*}] \
|
||
-to [get_cells -hierarchical -filter {NAME =~ *cic_*/comb_*reg*}]
|
||
set_multicycle_path 3 -hold \
|
||
-from [get_cells -hierarchical -filter {NAME =~ *cic_*/comb_*reg*}] \
|
||
-to [get_cells -hierarchical -filter {NAME =~ *cic_*/comb_*reg*}]
|
||
# Also relax the launch path from integrator_sampled_comb (fed by integrator_4
|
||
# DSP48E1 at decimated rate) into comb_0_c_reg.
|
||
set_multicycle_path 4 -setup \
|
||
-from [get_cells -hierarchical -filter {NAME =~ *cic_*/integrator_sampled_comb_reg*}] \
|
||
-to [get_cells -hierarchical -filter {NAME =~ *cic_*/comb_*reg*}]
|
||
set_multicycle_path 3 -hold \
|
||
-from [get_cells -hierarchical -filter {NAME =~ *cic_*/integrator_sampled_comb_reg*}] \
|
||
-to [get_cells -hierarchical -filter {NAME =~ *cic_*/comb_*reg*}]
|
||
|
||
# clk_100m ↔ clk_120m_dac: CDC via synchronizers in radar_system_top
|
||
set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_120m_dac]
|
||
set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m]
|
||
|
||
# FT2232H CDC: clk_100m ↔ ft_clkout (60 MHz), toggle CDC in RTL
|
||
set_false_path -from [get_clocks clk_100m] -to [get_clocks ft_clkout]
|
||
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
|
||
|
||
# FT2232H CDC: clk_120m_dac ↔ ft_clkout (no direct crossing, but belt-and-suspenders)
|
||
set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
|
||
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
|
||
|
||
# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
|
||
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
|
||
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
|
||
|
||
# ============================================================================
|
||
# PHYSICAL CONSTRAINTS
|
||
# ============================================================================
|
||
|
||
# Pull up unused pins to prevent floating inputs
|
||
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
|
||
|
||
# ============================================================================
|
||
# ADDITIONAL NOTES
|
||
# ============================================================================
|
||
#
|
||
# 1. ADC Sampling Clock: FPGA_ADC_CLOCK_P/N (N11/N12) is the 400 MHz LVDS
|
||
# clock from AD9523 OUT5 that drives the AD9484. It connects to FPGA MRCC
|
||
# pins but is not used as an FPGA clock input — the ADC returns data with
|
||
# its own DCO (adc_dco_p/n on N14/P14).
|
||
#
|
||
# 2. Clock Test: FPGA_CLOCK_TEST (H14) is a 20 MHz LVCMOS output from the
|
||
# FPGA, configured by AD9523 OUT7. Not currently used in RTL.
|
||
#
|
||
# 3. SPI Flash: FPGA_FLASH_CS (E8), FPGA_FLASH_CLK (J13),
|
||
# FPGA_FLASH_D0 (J14), D1 (K15), D2 (K16), D3 (L12), unnamed (L13).
|
||
# These are typically handled by Vivado bitstream configuration and do
|
||
# not need explicit XDC constraints for user logic.
|
||
#
|
||
# 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
|
||
# Dedicated pins — no XDC constraints needed.
|
||
#
|
||
# 5. dac_clk port: Not connected on the 50T board (DAC clocked directly from
|
||
# AD9523). The RTL port exists for 200T board compatibility, where the FPGA
|
||
# forwards the DAC clock via ODDR to pin H17 with generated clock and
|
||
# timing constraints (see xc7a200t_fbg484.xdc). Do NOT remove from RTL.
|
||
#
|
||
# ============================================================================
|
||
# END OF CONSTRAINTS
|
||
# ============================================================================
|