style(tests): fix ruff F401/E501 in test_ddc_cosim_fuzz

Drop unused os/tempfile imports; wrap three long lines to satisfy
E501 (100-col limit). No behavioral change.

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp

@@ -10,15 +10,15 @@ extern SPI_HandleTypeDef hspi1;
 extern UART_HandleTypeDef huart3;
 
 // Chip Select GPIO definitions
-static const struct {
-    GPIO_TypeDef* port;
-    uint16_t pin;
-} CHIP_SELECTS[4] = {
-    {ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
-    {ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
-    {ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
-    {ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin}  // ADAR1000 #4
-};
+static const struct {
+    GPIO_TypeDef* port;
+    uint16_t pin;
+} CHIP_SELECTS[4] = {
+    {ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
+    {ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
+    {ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
+    {ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin}  // ADAR1000 #4
+};
 
 // ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
 //
@@ -163,8 +163,10 @@ void ADAR1000Manager::switchToTXMode() {
     DIAG("BF", "Step 3: PA bias ON");
     setPABias(true);
     delayUs(50);
-    DIAG("BF", "Step 4: ADTR1107 -> TX");
-    setADTR1107Control(true);
+    // Step 4 (former setADTR1107Control(true)) removed: TR pin is FPGA-owned.
+    // Chip follows adar_tr_x; TX path is asserted by the FPGA chirp FSM, not
+    // by SPI here. Write per-channel TX enables so the FPGA TR override has
+    // something to gate.
 
     for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
         adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
@@ -185,8 +187,7 @@ void ADAR1000Manager::switchToRXMode() {
     DIAG("BF", "Step 2: Disable PA supplies");
     disablePASupplies();
     delayUs(10);
-    DIAG("BF", "Step 3: ADTR1107 -> RX");
-    setADTR1107Control(false);
+    // Step 3 (former setADTR1107Control(false)) removed: FPGA owns TR pin.
     DIAG("BF", "Step 4: Enable LNA supplies");
     enableLNASupplies();
     delayUs(50);
@@ -204,39 +205,11 @@ void ADAR1000Manager::switchToRXMode() {
     DIAG("BF", "switchToRXMode() complete");
 }
 
-void ADAR1000Manager::fastTXMode() {
-    DIAG("BF", "fastTXMode(): ADTR1107 -> TX (no bias sequencing)");
-    setADTR1107Control(true);
-    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-        adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
-        adarWrite(dev, REG_TX_ENABLES, 0x0F, BROADCAST_OFF);
-        devices_[dev]->current_mode = BeamDirection::TX;
-    }
-    current_mode_ = BeamDirection::TX;
-}
-
-void ADAR1000Manager::fastRXMode() {
-    DIAG("BF", "fastRXMode(): ADTR1107 -> RX (no bias sequencing)");
-    setADTR1107Control(false);
-    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-        adarWrite(dev, REG_TX_ENABLES, 0x00, BROADCAST_OFF);
-        adarWrite(dev, REG_RX_ENABLES, 0x0F, BROADCAST_OFF);
-        devices_[dev]->current_mode = BeamDirection::RX;
-    }
-    current_mode_ = BeamDirection::RX;
-}
-
-void ADAR1000Manager::pulseTXMode() {
-    DIAG("BF", "pulseTXMode(): TR switch only");
-    setADTR1107Control(true);
-    last_switch_time_us_ = HAL_GetTick() * 1000;
-}
-
-void ADAR1000Manager::pulseRXMode() {
-    DIAG("BF", "pulseRXMode(): TR switch only");
-    setADTR1107Control(false);
-    last_switch_time_us_ = HAL_GetTick() * 1000;
-}
+// fastTXMode, fastRXMode, pulseTXMode, pulseRXMode: REMOVED.
+// The chirp hot path owns T/R switching via the FPGA adar_tr_x pins
+// (see 9_Firmware/9_2_FPGA/plfm_chirp_controller.v). The old SPI-RMW per
+// chirp was architecturally redundant, raced the FPGA, and toggled the
+// wrong bit of REG_SW_CONTROL (TR_SOURCE instead of TR_SPI).
 
 // Beam Steering
 bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction) {
@@ -255,15 +228,15 @@ bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction)
 
     for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
         for (uint8_t ch = 0; ch < 4; ++ch) {
-            if (direction == BeamDirection::TX) {
-                adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
-                adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
-            } else {
-                adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
-                adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
-            }
-        }
-    }
+            if (direction == BeamDirection::TX) {
+                adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
+                adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
+            } else {
+                adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
+                adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
+            }
+        }
+    }
     return true;
 }
 
@@ -368,25 +341,10 @@ void ADAR1000Manager::writeRegister(uint8_t deviceIndex, uint32_t address, uint8
 }
 
 // Configuration
-void ADAR1000Manager::setSwitchSettlingTime(uint32_t us) {
-    switch_settling_time_us_ = us;
-}
-
-void ADAR1000Manager::setFastSwitchMode(bool enable) {
-    DIAG("BF", "setFastSwitchMode(%s)", enable ? "ON" : "OFF");
-    fast_switch_mode_ = enable;
-    if (enable) {
-        switch_settling_time_us_ = 10;
-        DIAG("BF", "  settling time = 10 us, enabling PA+LNA supplies and bias simultaneously");
-        enablePASupplies();
-        enableLNASupplies();
-        setPABias(true);
-        setLNABias(true);
-    } else {
-        switch_settling_time_us_ = 50;
-        DIAG("BF", "  settling time = 50 us");
-    }
-}
+// setSwitchSettlingTime, setFastSwitchMode: REMOVED.
+// Their only reader was the deleted setADTR1107Control; setFastSwitchMode(true)
+// also violated the ADTR1107 datasheet bias sequence (PA + LNA biased to
+// operational simultaneously). Per-chirp T/R is FPGA-owned now.
 
 void ADAR1000Manager::setBeamDwellTime(uint32_t ms) {
     beam_dwell_time_ms_ = ms;
@@ -428,15 +386,30 @@ bool ADAR1000Manager::initializeSingleDevice(uint8_t deviceIndex) {
     DIAG("BF", "  dev[%u] set RAM bypass (bias+beam)", deviceIndex);
     adarSetRamBypass(deviceIndex, BROADCAST_OFF);
 
+    // Hand per-chirp T/R switching to the FPGA.
+    // Set TR_SOURCE (REG_SW_CONTROL bit 2) = 1 so the chip's internal
+    // RX_EN_OVERRIDE / TX_EN_OVERRIDE follow the external TR pin (driven by
+    // plfm_chirp_controller's adar_tr_x output). See ADAR1000 datasheet
+    // "Theory of Operation" -- SPI Control vs TR Pin Control.
+    // Without this write, the FPGA's TR pin is ignored and the chip stays
+    // in RX state (TR_SPI POR default).
+    DIAG("BF", "  dev[%u] SW_CONTROL: TR_SOURCE=1 (FPGA owns TR pin)", deviceIndex);
+    adarWrite(deviceIndex, REG_SW_CONTROL, (1 << 2), BROADCAST_OFF);
+
     // Initialize ADC
     DIAG("BF", "  dev[%u] enable ADC (2MHz clk)", deviceIndex);
     adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN, BROADCAST_OFF);
 
     // Verify communication with scratchpad test
+    // Audit F-4.4: on SPI failure, previously marked the device initialized
+    // anyway, so downstream (e.g. PA enable) could drive PA gates out-of-spec
+    // on a dead bus. Now propagate the failure so initializeAllDevices aborts.
     DIAG("BF", "  dev[%u] verifying SPI communication...", deviceIndex);
     bool comms_ok = verifyDeviceCommunication(deviceIndex);
     if (!comms_ok) {
-        DIAG_WARN("BF", "  dev[%u] scratchpad verify FAILED but marking initialized anyway", deviceIndex);
+        DIAG_ERR("BF", "  dev[%u] scratchpad verify FAILED -- device NOT marked initialized", deviceIndex);
+        devices_[deviceIndex]->initialized = false;
+        return false;
     }
 
     devices_[deviceIndex]->initialized = true;
@@ -464,9 +437,11 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
     HAL_GPIO_WritePin(EN_P_3V3_SW_GPIO_Port, EN_P_3V3_SW_Pin, GPIO_PIN_SET);
     HAL_Delay(1);
 
-    // Step 4: Set CTRL_SW to RX mode initially via GPIO
-    DIAG("BF", "Step 4: CTRL_SW -> RX (initial safe mode)");
-    setADTR1107Control(false); // RX mode
+    // Step 4: CTRL_SW safe-default is RX.
+    // FPGA-owned path: with TR_SOURCE=1 (set in initializeSingleDevice) the
+    // chip follows adar_tr_x, which is 0 in the FPGA FSM's IDLE state = RX.
+    // No SPI write needed here.
+    DIAG("BF", "Step 4: CTRL_SW -> RX (FPGA adar_tr_x idle-low == RX)");
     HAL_Delay(1);
 
     // Step 5: Set VGG_LNA to 0
@@ -522,7 +497,7 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
     HAL_UART_Transmit(&huart3, success, sizeof(success) - 1, 1000);
 
     return true;
-}
+}
 
 bool ADAR1000Manager::setAllDevicesTXMode() {
     DIAG("BF", "setAllDevicesTXMode(): ADTR1107 -> TX, then configure ADAR1000s");
@@ -568,7 +543,7 @@ bool ADAR1000Manager::setAllDevicesRXMode() {
 void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
     if (direction == BeamDirection::TX) {
         DIAG_SECTION("ADTR1107 -> TX MODE");
-        setADTR1107Control(true); // TX mode
+        // setADTR1107Control(true) removed: TR pin is FPGA-driven.
 
         // Step 1: Disable LNA power first
         DIAG("BF", "  Disable LNA supplies");
@@ -598,10 +573,11 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
         }
         HAL_Delay(5);
 
-        // Step 5: Set TR switch to TX mode
-        DIAG("BF", "  TR switch -> TX (TR_SOURCE=1, BIAS_EN)");
+        // Step 5: TR switch state is FPGA-driven. TR_SOURCE=1 is set once in
+        // initializeSingleDevice, so the chip already follows adar_tr_x.
+        // Only BIAS_EN needs to be asserted here.
+        DIAG("BF", "  BIAS_EN (TR source still = FPGA adar_tr_x)");
         for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-            adarSetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 1 (TX)
             adarSetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF); // BIAS_EN
         }
         DIAG("BF", "  ADTR1107 TX mode complete");
@@ -609,7 +585,7 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
     } else {
         // RECEIVE MODE: Enable LNA, Disable PA
         DIAG_SECTION("ADTR1107 -> RX MODE");
-        setADTR1107Control(false); // RX mode
+        // setADTR1107Control(false) removed: TR pin is FPGA-driven.
 
         // Step 1: Disable PA power first
         DIAG("BF", "  Disable PA supplies");
@@ -640,34 +616,21 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
         }
         HAL_Delay(5);
 
-        // Step 5: Set TR switch to RX mode
-        DIAG("BF", "  TR switch -> RX (TR_SOURCE=0, LNA_BIAS_OUT_EN)");
+        // Step 5: TR switch state is FPGA-driven (TR_SOURCE left at 1).
+        // Only LNA_BIAS_OUT_EN needs to be asserted here.
+        DIAG("BF", "  LNA_BIAS_OUT_EN (TR source still = FPGA adar_tr_x)");
         for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-            adarResetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 0 (RX)
             adarSetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF); // LNA_BIAS_OUT_EN
         }
         DIAG("BF", "  ADTR1107 RX mode complete");
     }
-}
-
-void ADAR1000Manager::setADTR1107Control(bool tx_mode) {
-    DIAG("BF", "setADTR1107Control(%s): setting TR switch on all %u devices, settling %lu us",
-         tx_mode ? "TX" : "RX", (unsigned)devices_.size(), (unsigned long)switch_settling_time_us_);
-    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-        setTRSwitchPosition(dev, tx_mode);
-    }
-    delayUs(switch_settling_time_us_);
 }
 
-void ADAR1000Manager::setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode) {
-    if (tx_mode) {
-        // TX mode: Set TR_SOURCE = 1
-        adarSetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
-    } else {
-        // RX mode: Set TR_SOURCE = 0
-        adarResetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
-    }
-}
+// setADTR1107Control, setTRSwitchPosition: REMOVED.
+// The per-device SPI RMW of REG_SW_CONTROL bit 2 (TR_SOURCE) was both wrong
+// (it toggled the *control source*, not the TX/RX state -- TR_SPI is bit 1)
+// and redundant with the FPGA's plfm_chirp_controller adar_tr_x output.
+// TR_SOURCE is now set to 1 exactly once in initializeSingleDevice.
 
 // Add the new public method
 bool ADAR1000Manager::setCustomBeamPattern16(const uint8_t phase_pattern[16], BeamDirection direction) {
@@ -727,13 +690,24 @@ void ADAR1000Manager::setLNABias(bool enable) {
     for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
         adarWrite(dev, REG_LNA_BIAS_ON, lna_bias, BROADCAST_OFF);
     }
-}
+}
 
 void ADAR1000Manager::delayUs(uint32_t microseconds) {
-    // Simple implementation - for F7 @ 216MHz, each loop ~7 cycles ≈ 0.032us
-    volatile uint32_t cycles = microseconds * 10; // Adjust this multiplier for your clock
-    while (cycles--) {
-        __NOP();
+    // Audit F-4.7: the prior implementation was a calibrated __NOP() busy-loop
+    // that silently drifted with compiler optimization, cache state, and flash
+    // wait-states. The ADAR1000 PLL/TX settling times require a real clock, so
+    // we poll the DWT cycle counter instead. One-time TRCENA/CYCCNTENA enable
+    // is idempotent; subsequent calls skip the init branch via DWT->CTRL read.
+    if ((DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) == 0U) {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        DWT->CYCCNT       = 0U;
+        DWT->CTRL        |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+    const uint32_t cycles_per_us = SystemCoreClock / 1000000U;
+    const uint32_t start         = DWT->CYCCNT;
+    const uint32_t target        = microseconds * cycles_per_us;
+    while ((DWT->CYCCNT - start) < target) {
+        /* CYCCNT wraps cleanly modulo 2^32 — subtraction stays correct. */
     }
 }
 
@@ -795,14 +769,25 @@ void ADAR1000Manager::setChipSelect(uint8_t deviceIndex, bool state) {
 }
 
 void ADAR1000Manager::adarWrite(uint8_t deviceIndex, uint32_t mem_addr, uint8_t data, uint8_t broadcast) {
-    uint8_t instruction[3];
-
-    if (broadcast) {
-        instruction[0] = 0x08;
-    } else {
-        instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
+    // Audit F-4.1: the broadcast SPI opcode path (`instruction[0] = 0x08`)
+    // has never been exercised on silicon and is structurally questionable —
+    // setChipSelect() only toggles ONE device's CS line, so even if a caller
+    // opts into the broadcast opcode today, only the single selected chip
+    // actually sees the frame. Until a HIL test confirms multi-CS semantics,
+    // route every broadcast write through a per-device unicast loop. This
+    // preserves caller intent (all four devices take the write) and makes
+    // the dead opcode-0x08 path unreachable at runtime.
+    if (broadcast == BROADCAST_ON) {
+        DIAG_WARN("BF", "adarWrite: broadcast=1 lowered to per-device unicast (addr=0x%03lX data=0x%02X)",
+                  (unsigned long)mem_addr, data);
+        for (uint8_t d = 0; d < devices_.size(); ++d) {
+            adarWrite(d, mem_addr, data, BROADCAST_OFF);
+        }
+        return;
     }
 
+    uint8_t instruction[3];
+    instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
     instruction[0] |= (0x1F00 & mem_addr) >> 8;
     instruction[1] = (0xFF & mem_addr);
     instruction[2] = data;
@@ -835,12 +820,26 @@ uint8_t ADAR1000Manager::adarRead(uint8_t deviceIndex, uint32_t mem_addr) {
 }
 
 void ADAR1000Manager::adarSetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
+    // Audit F-4.2: broadcast-RMW is unsafe. The read samples a single device
+    // but the write fans out to all four, overwriting the other three with
+    // deviceIndex's state. Reject and surface the mistake.
+    if (broadcast == BROADCAST_ON) {
+        DIAG_ERR("BF", "adarSetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
+                 deviceIndex, (unsigned long)mem_addr, bit);
+        return;
+    }
     uint8_t temp = adarRead(deviceIndex, mem_addr);
     uint8_t data = temp | (1 << bit);
     adarWrite(deviceIndex, mem_addr, data, broadcast);
 }
 
 void ADAR1000Manager::adarResetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
+    // Audit F-4.2: see adarSetBit.
+    if (broadcast == BROADCAST_ON) {
+        DIAG_ERR("BF", "adarResetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
+                 deviceIndex, (unsigned long)mem_addr, bit);
+        return;
+    }
     uint8_t temp = adarRead(deviceIndex, mem_addr);
     uint8_t data = temp & ~(1 << bit);
     adarWrite(deviceIndex, mem_addr, data, broadcast);
@@ -868,11 +867,22 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
 }
 
 void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
+    // channel is 1-based (CH1..CH4) per API contract documented in
+    // ADAR1000_AGC.cpp and matching ADI datasheet terminology.
+    // Reject out-of-range early so a stale 0-based caller does not
+    // silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
+    // See issue #90.
+    if (channel < 1 || channel > 4) {
+        DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
+        return;
+    }
     uint8_t i_val = VM_I[phase % 128];
     uint8_t q_val = VM_Q[phase % 128];
 
-    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
+    // Subtract 1 to convert 1-based channel to 0-based register offset
+    // before masking. See issue #90.
+    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
 
     adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
     adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -880,34 +890,49 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }
 
 void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
+    // channel is 1-based (CH1..CH4). See issue #90.
+    if (channel < 1 || channel > 4) {
+        DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
+        return;
+    }
     uint8_t i_val = VM_I[phase % 128];
     uint8_t q_val = VM_Q[phase % 128];
 
-    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
 
     adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
     adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
-    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
+    adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
 
 void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
+    // channel is 1-based (CH1..CH4). See issue #90.
+    if (channel < 1 || channel > 4) {
+        DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
+        return;
+    }
+    uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
     adarWrite(deviceIndex, mem_addr, gain, broadcast);
     adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
 }
 
 void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
+    // channel is 1-based (CH1..CH4). See issue #90.
+    if (channel < 1 || channel > 4) {
+        DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
+        return;
+    }
+    uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
     adarWrite(deviceIndex, mem_addr, gain, broadcast);
     adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
 
-void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
-    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
-    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
-    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
-}
+void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
+    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
+    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
+    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
+}
 
 uint8_t ADAR1000Manager::adarAdcRead(uint8_t deviceIndex, uint8_t broadcast) {
     adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h

@@ -48,10 +48,11 @@ public:
     // Mode Switching
     void switchToTXMode();
     void switchToRXMode();
-    void fastTXMode();
-    void fastRXMode();
-    void pulseTXMode();
-    void pulseRXMode();
+    // fastTXMode/fastRXMode/pulseTXMode/pulseRXMode were removed: per-chirp T/R
+    // switching is owned by the FPGA (plfm_chirp_controller -> adar_tr_x pins,
+    // requires TR_SOURCE=1 in REG_SW_CONTROL, set in initializeSingleDevice).
+    // The old SPI RMW path was architecturally redundant and also toggled the
+    // wrong bit (TR_SOURCE instead of TR_SPI). See PR for details.
 
     // Beam Steering
     bool setBeamAngle(float angle_degrees, BeamDirection direction);
@@ -69,7 +70,8 @@ public:
     bool setAllDevicesTXMode();
     bool setAllDevicesRXMode();
     void setADTR1107Mode(BeamDirection direction);
-    void setADTR1107Control(bool tx_mode);
+    // setADTR1107Control removed -- it only wrapped the now-deleted
+    // setTRSwitchPosition SPI path. FPGA drives the TR pin directly.
 
     // Monitoring and Diagnostics
     float readTemperature(uint8_t deviceIndex);
@@ -78,8 +80,11 @@ public:
     void writeRegister(uint8_t deviceIndex, uint32_t address, uint8_t value);
 
     // Configuration
-    void setSwitchSettlingTime(uint32_t us);
-    void setFastSwitchMode(bool enable);
+    // setSwitchSettlingTime / setFastSwitchMode removed: their only reader was
+    // the deleted setADTR1107Control SPI path, and setFastSwitchMode(true)
+    // also bundled a datasheet-violating PA+LNA-biased-simultaneously side
+    // effect. Per-chirp settling is now FPGA-owned. Callers that need a
+    // warm-up bias state should use switchToTXMode / switchToRXMode instead.
     void setBeamDwellTime(uint32_t ms);
 
     // Getters
@@ -100,8 +105,8 @@ public:
     };
 
     // Configuration
-    bool fast_switch_mode_ = false;
-    uint32_t switch_settling_time_us_ = 50;
+    // fast_switch_mode_ / switch_settling_time_us_ removed: both had no
+    // readers after the FPGA-owned TR refactor.
     uint32_t beam_dwell_time_ms_ = 100;
     uint32_t last_switch_time_us_ = 0;
 
@@ -121,22 +126,22 @@ public:
     // No VM_GAIN[] table exists: VM magnitude is bits [4:0] of the I/Q bytes
     // themselves; per-channel VGA gain uses a separate register.
     static const uint8_t VM_I[128];
-    static const uint8_t VM_Q[128];
-
-    // Named defaults for the ADTR1107 and ADAR1000 power sequence.
-    static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
-    static constexpr uint8_t kDefaultRxVgaGain = 30;
-    static constexpr uint8_t kLnaBiasOff = 0x00;
-    static constexpr uint8_t kLnaBiasOperational = 0x30;
-    static constexpr uint8_t kPaBiasTxSafe = 0x5D;
-    static constexpr uint8_t kPaBiasIdqCalibration = 0x0D;
-    static constexpr uint8_t kPaBiasOperational = 0x7F;
-    static constexpr uint8_t kPaBiasRxSafe = 0x20;
-    static constexpr uint8_t kTxBiasCurrent = 0x2D;
-    static constexpr uint8_t kTxDriverBiasCurrent = 0x06;
-
-    // Private Methods
-    bool initializeSingleDevice(uint8_t deviceIndex);
+    static const uint8_t VM_Q[128];
+
+    // Named defaults for the ADTR1107 and ADAR1000 power sequence.
+    static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
+    static constexpr uint8_t kDefaultRxVgaGain = 30;
+    static constexpr uint8_t kLnaBiasOff = 0x00;
+    static constexpr uint8_t kLnaBiasOperational = 0x30;
+    static constexpr uint8_t kPaBiasTxSafe = 0x5D;
+    static constexpr uint8_t kPaBiasIdqCalibration = 0x0D;
+    static constexpr uint8_t kPaBiasOperational = 0x7F;
+    static constexpr uint8_t kPaBiasRxSafe = 0x20;
+    static constexpr uint8_t kTxBiasCurrent = 0x2D;
+    static constexpr uint8_t kTxDriverBiasCurrent = 0x06;
+
+    // Private Methods
+    bool initializeSingleDevice(uint8_t deviceIndex);
     bool initializeADTR1107Sequence();
     void calculatePhaseSettings(float angle_degrees, uint8_t phase_settings[4]);
     void delayUs(uint32_t microseconds);
@@ -167,7 +172,7 @@ public:
     void adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast);
     void adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast);
     uint8_t adarAdcRead(uint8_t deviceIndex, uint8_t broadcast);
-    void setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode);
+    // setTRSwitchPosition removed -- FPGA owns TR pin. See PR.
 
 private:
 

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -483,11 +483,14 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
     DIAG("SYS", "executeChirpSequence: num_chirps=%d T1=%.2f PRI1=%.2f T2=%.2f PRI2=%.2f",
          num_chirps, T1, PRI1, T2, PRI2);
     // First chirp sequence (microsecond timing)
+    // T/R switching is owned by the FPGA plfm_chirp_controller: its chirp
+    // FSM drives adar_tr_x high during LONG_CHIRP/SHORT_CHIRP and low during
+    // listen/guard. new_chirp (GPIOD_8) triggers the FSM out of IDLE.
+    // The MCU's old pulseTXMode/pulseRXMode SPI path was redundant and raced
+    // the FPGA -- removed.
     for(int i = 0; i < num_chirps; i++) {
         HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
-        adarManager.pulseTXMode();
         delay_us((uint32_t)T1);
-        adarManager.pulseRXMode();
         delay_us((uint32_t)(PRI1 - T1));
     }
 
@@ -496,11 +499,8 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
     // Second chirp sequence (nanosecond timing)
     for(int i = 0; i < num_chirps; i++) {
     	HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
-        adarManager.pulseTXMode();
         delay_ns((uint32_t)(T2 * 1000));
-        adarManager.pulseRXMode();
         delay_ns((uint32_t)((PRI2 - T2) * 1000));
-
     }
 }
 
@@ -513,9 +513,9 @@ void runRadarPulseSequence() {
     DIAG("SYS", "runRadarPulseSequence #%d: m_max=%d n_max=%d y_max=%d",
          sequence_count, m_max, n_max, y_max);
 
-    // Configure for fast switching
-    DIAG("BF", "Enabling fast-switch mode for beam sweep");
-    adarManager.setFastSwitchMode(true);
+    // Fast per-chirp switching is now FPGA-owned (plfm_chirp_controller
+    // adar_tr_x), not MCU-driven. setFastSwitchMode(true) call removed.
+    DIAG("BF", "Beam sweep start (FPGA owns per-chirp T/R switching)");
 
     int m = 1; // Chirp counter
     int n = 1; // Beam Elevation position counter
@@ -656,18 +656,18 @@ SystemError_t checkSystemHealth(void) {
 
     // 1. Check AD9523 Clock Generator
     static uint32_t last_clock_check = 0;
-    if (HAL_GetTick() - last_clock_check > 5000) {
-        GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
-        GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
-        DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
-        DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
-        if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
-            current_error = ERROR_AD9523_CLOCK;
-            DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
-            return current_error;
-        }
-        last_clock_check = HAL_GetTick();
-    }
+    if (HAL_GetTick() - last_clock_check > 5000) {
+        GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
+        GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
+        DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
+        DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
+        if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
+            current_error = ERROR_AD9523_CLOCK;
+            DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
+            return current_error;
+        }
+        last_clock_check = HAL_GetTick();
+    }
 
     // 2. Check ADF4382 Lock Status
     bool tx_locked, rx_locked;
@@ -702,34 +702,34 @@ SystemError_t checkSystemHealth(void) {
 
     // 4. Check IMU Communication
     static uint32_t last_imu_check = 0;
-    if (HAL_GetTick() - last_imu_check > 10000) {
-        if (!GY85_Update(&imu)) {
-            current_error = ERROR_IMU_COMM;
-            DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
-            return current_error;
-        }
-        last_imu_check = HAL_GetTick();
-    }
+    if (HAL_GetTick() - last_imu_check > 10000) {
+        if (!GY85_Update(&imu)) {
+            current_error = ERROR_IMU_COMM;
+            DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
+            return current_error;
+        }
+        last_imu_check = HAL_GetTick();
+    }
 
     // 5. Check BMP180 Communication
     static uint32_t last_bmp_check = 0;
-    if (HAL_GetTick() - last_bmp_check > 15000) {
-        double pressure = myBMP.getPressure();
-        if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
-            current_error = ERROR_BMP180_COMM;
-            DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
-            return current_error;
-        }
-        last_bmp_check = HAL_GetTick();
-    }
+    if (HAL_GetTick() - last_bmp_check > 15000) {
+        double pressure = myBMP.getPressure();
+        if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
+            current_error = ERROR_BMP180_COMM;
+            DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
+            return current_error;
+        }
+        last_bmp_check = HAL_GetTick();
+    }
 
-    // 6. Check GPS Communication (30s grace period from boot / last valid fix)
-    uint32_t gps_fix_age = um982_position_age(&um982);
-    if (gps_fix_age > 30000) {
-        current_error = ERROR_GPS_COMM;
-        DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
-        return current_error;
-    }
+    // 6. Check GPS Communication (30s grace period from boot / last valid fix)
+    uint32_t gps_fix_age = um982_position_age(&um982);
+    if (gps_fix_age > 30000) {
+        current_error = ERROR_GPS_COMM;
+        DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
+        return current_error;
+    }
 
     // 7. Check RF Power Amplifier Current
     if (PowerAmplifier) {
@@ -760,7 +760,7 @@ SystemError_t checkSystemHealth(void) {
         DIAG_ERR("SYS", "checkSystemHealth returning error code %d", current_error);
     }
     return current_error;
-}
+}
 
 // Error recovery function
 void attemptErrorRecovery(SystemError_t error) {
@@ -905,22 +905,22 @@ void handleSystemError(SystemError_t error) {
         HAL_Delay(200);
     }
 
-    // Critical errors trigger emergency shutdown.
-    //
-    // Safety-critical range: any fault that can damage the PAs or leave the
-    // system in an undefined state must cut the RF rails via Emergency_Stop().
-    // This covers:
-    //   ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
-    //   ERROR_TEMPERATURE_HIGH  (14) -- >75 C on the PA thermal sensors;
-    //                                  without cutting bias + 5V/5V5/RFPA rails
-    //                                  the GaN QPA2962 stage can thermal-runaway.
-    //   ERROR_WATCHDOG_TIMEOUT  (16) -- health-check loop has stalled (>60 s);
-    //                                  transmitter state is unknown, safest to
-    //                                  latch Emergency_Stop rather than rely on
-    //                                  IWDG reset (which re-energises the rails).
-    if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
-        error == ERROR_TEMPERATURE_HIGH ||
-        error == ERROR_WATCHDOG_TIMEOUT) {
+    // Critical errors trigger emergency shutdown.
+    //
+    // Safety-critical range: any fault that can damage the PAs or leave the
+    // system in an undefined state must cut the RF rails via Emergency_Stop().
+    // This covers:
+    //   ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
+    //   ERROR_TEMPERATURE_HIGH  (14) -- >75 C on the PA thermal sensors;
+    //                                  without cutting bias + 5V/5V5/RFPA rails
+    //                                  the GaN QPA2962 stage can thermal-runaway.
+    //   ERROR_WATCHDOG_TIMEOUT  (16) -- health-check loop has stalled (>60 s);
+    //                                  transmitter state is unknown, safest to
+    //                                  latch Emergency_Stop rather than rely on
+    //                                  IWDG reset (which re-energises the rails).
+    if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
+        error == ERROR_TEMPERATURE_HIGH ||
+        error == ERROR_WATCHDOG_TIMEOUT) {
         DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, err_name);
         snprintf(error_msg, sizeof(error_msg),
                  "CRITICAL ERROR! Initiating emergency shutdown.\r\n");
@@ -1483,8 +1483,8 @@ int main(void)
   HAL_GPIO_WritePin(EN_P_3V3_FPGA_GPIO_Port,EN_P_3V3_FPGA_Pin,GPIO_PIN_SET);
   HAL_Delay(100);
   DIAG("PWR", "FPGA power sequencing complete -- 1.0V -> 1.8V -> 3.3V");
-
-
+
+
 // Initialize module IMU
   DIAG_SECTION("IMU INIT (GY-85)");
   DIAG("IMU", "Initializing GY-85 IMU...");
@@ -1493,12 +1493,12 @@ int main(void)
       Error_Handler();
   }
   DIAG("IMU", "GY-85 initialized OK, running 10 calibration samples");
-  for(int i=0; i<10;i++){
-  if (!GY85_Update(&imu)) {
-      Error_Handler();
-  }
-
-  ax = imu.ax;
+  for(int i=0; i<10;i++){
+  if (!GY85_Update(&imu)) {
+      Error_Handler();
+  }
+
+  ax = imu.ax;
   ay = imu.ay;
   az = imu.az;
   gx = -imu.gx;
@@ -1793,20 +1793,20 @@ int main(void)
           HAL_Delay(10);
       }
   }
-  RADAR_Longitude = um982_get_longitude(&um982);
-  RADAR_Latitude = um982_get_latitude(&um982);
-  DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
-       RADAR_Latitude, RADAR_Longitude,
-       um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
-
-  // Re-apply heading after GPS init so the north-alignment stepper move uses
-  // UM982 dual-antenna heading when available.
-  if (um982_is_heading_valid(&um982)) {
-      Yaw_Sensor = um982_get_heading(&um982);
-  }
-
-  //move Stepper to position 1 = 0°
-  HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
+  RADAR_Longitude = um982_get_longitude(&um982);
+  RADAR_Latitude = um982_get_latitude(&um982);
+  DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
+       RADAR_Latitude, RADAR_Longitude,
+       um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
+
+  // Re-apply heading after GPS init so the north-alignment stepper move uses
+  // UM982 dual-antenna heading when available.
+  if (um982_is_heading_valid(&um982)) {
+      Yaw_Sensor = um982_get_heading(&um982);
+  }
+
+  //move Stepper to position 1 = 0°
+  HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
   //Point Stepper to North
   for(int i= 0;i<(int)(Yaw_Sensor*Stepper_steps/360);i++){
 	  HAL_GPIO_WritePin(STEPPER_CLK_P_GPIO_Port, STEPPER_CLK_P_Pin, GPIO_PIN_SET);
@@ -1819,14 +1819,14 @@ int main(void)
   /**********wait for GUI start flag and Send Lat/Long/alt********/
   /***************************************************************/
 
-  GPS_Data_t gps_data;
-  // Binary packet structure:
-  // [Header 4 bytes][Latitude 8 bytes][Longitude 8 bytes][Altitude 4 bytes][Pitch 4 bytes][CRC 2 bytes]
-  gps_data = {RADAR_Latitude, RADAR_Longitude, RADAR_Altitude, Pitch_Sensor, HAL_GetTick()};
-  if (!GPS_SendBinaryToGUI(&gps_data)) {
-      const uint8_t gps_send_error[] = "GPS binary send failed\r\n";
-      HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
-  }
+  GPS_Data_t gps_data;
+  // Binary packet structure:
+  // [Header 4 bytes][Latitude 8 bytes][Longitude 8 bytes][Altitude 4 bytes][Pitch 4 bytes][CRC 2 bytes]
+  gps_data = {RADAR_Latitude, RADAR_Longitude, RADAR_Altitude, Pitch_Sensor, HAL_GetTick()};
+  if (!GPS_SendBinaryToGUI(&gps_data)) {
+      const uint8_t gps_send_error[] = "GPS binary send failed\r\n";
+      HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
+  }
 
   /* [STM32-006 FIXED] Removed blocking do-while loop that waited for
    * usbHandler.isStartFlagReceived().  The production V7 PyQt GUI does not

9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.c

@@ -406,3 +406,11 @@ static int mock_spi_init_stub(void) { return 0; }
 const struct no_os_spi_platform_ops stm32_spi_ops = {
     .init = mock_spi_init_stub,
 };
+
+/* ========================= CMSIS-Core stub storage ======================= */
+/* See stm32_hal_mock.h for rationale. SystemCoreClock = 0 forces delayUs() to
+ * return immediately under host test builds. DWT->CTRL pre-enabled so the
+ * one-time-init branch is skipped deterministically. */
+struct _DWT_Mock_Type       _dwt_mock       = { .CTRL = DWT_CTRL_CYCCNTENA_Msk, .CYCCNT = 0 };
+struct _CoreDebug_Mock_Type _coredebug_mock = { .DEMCR = 0 };
+uint32_t                    SystemCoreClock = 0U;

9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h

@@ -242,6 +242,26 @@ uint8_t ADS7830_Measure_SingleEnded(ADC_HandleTypeDef *hadc, uint8_t channel);
  * if desired via a global flag. */
 extern int mock_printf_enabled;
 
+/* ========================= CMSIS-Core stubs ======================= */
+/* Minimum surface to let F-4.7's DWT-based delayUs() in ADAR1000_Manager.cpp
+ * compile under the host mock build. SystemCoreClock is intentionally 0 so
+ * target = microseconds * (SystemCoreClock / 1000000) is also 0, making the
+ * busy-wait loop exit immediately regardless of argument. Pre-setting
+ * DWT->CTRL with CYCCNTENA also skips the one-time init branch.            */
+
+#define DWT_CTRL_CYCCNTENA_Msk     (1UL << 0)
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24)
+
+struct _DWT_Mock_Type       { uint32_t CTRL; uint32_t CYCCNT; };
+struct _CoreDebug_Mock_Type { uint32_t DEMCR; };
+
+extern struct _DWT_Mock_Type       _dwt_mock;
+extern struct _CoreDebug_Mock_Type _coredebug_mock;
+extern uint32_t                    SystemCoreClock;
+
+#define DWT       (&_dwt_mock)
+#define CoreDebug (&_coredebug_mock)
+
 #ifdef __cplusplus
 }
 #endif

9_Firmware/9_2_FPGA/.gitignore

@@ -3,6 +3,13 @@
 *.vcd
 tb/*.vvp
 tb/*.vcd
+a.out
+
+# Test-run outputs (written by testbenches, not oracles/stimulus).
+# NOTE: golden references (.hex, .mem, doppler_golden_py_*.csv) ARE
+# committed — they are load-bearing oracles for MF/Doppler/receiver
+# cosim tests. Only TB-written CSV outputs are ignored here.
+tb/cosim/rx_final_doppler_out.csv
 
 # Vivado project files (managed separately)
 *.jou

9_Firmware/9_2_FPGA/ad9484_interface_400m.v

@@ -4,15 +4,23 @@ module ad9484_interface_400m (
     input wire [7:0] adc_d_n,        // ADC Data N
     input wire adc_dco_p,            // Data Clock Output P (400MHz)
     input wire adc_dco_n,            // Data Clock Output N (400MHz)
-    
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair, DDR like data.
+    // Routed on the 50T main board to bank 14 pins M6/N6. Asserts for any
+    // sample whose absolute value exceeds full-scale.
+    input wire adc_or_p,
+    input wire adc_or_n,
+
     // System Interface
     input wire sys_clk,              // 100MHz system clock (for control only)
     input wire reset_n,
-    
+
     // Output at 400MHz domain
     output wire [7:0] adc_data_400m, // ADC data at 400MHz
     output wire adc_data_valid_400m, // Valid at 400MHz
-    output wire adc_dco_bufg         // Buffered 400MHz DCO clock for downstream use
+    output wire adc_dco_bufg,        // Buffered 400MHz DCO clock for downstream use
+    // Audit F-0.1: OR flag, clk_400m domain. High on any sample in the
+    // current 400 MHz cycle where the ADC reports overrange.
+    output wire adc_overrange_400m
 );
 
 // LVDS to single-ended conversion
@@ -110,6 +118,14 @@ endgenerate
 // frequency-matched. This single register stage transfers from IOB (BUFIO)
 // to fabric (BUFG) with guaranteed timing.
 // ============================================================================
+// Timing on the BUFIO→BUFG CDC edge is governed by a 3.000 ns
+// set_max_delay in constraints/adc_clk_mmcm.xdc (1.2× the 2.500 ns period),
+// which leaves the placer free and still fits inside the ADC data-valid
+// window. IOB=TRUE and a pblock around the IDDR column were both tried
+// and rejected: IOB packing fails because the BUFG clock on these
+// capture FFs can't share the ILOGIC clock mux with the BUFIO-clocked
+// IDDR, and the pblock pulled fanout logic into the I/O region and
+// triggered router congestion on 51 unrelated paths.
 reg [7:0] adc_data_rise_bufg;
 reg [7:0] adc_data_fall_bufg;
 
@@ -131,9 +147,24 @@ reg dco_phase;
 //
 // mmcm_locked gates de-assertion: the 400 MHz domain stays in reset until
 // the MMCM PLL has locked and the jitter-cleaned clock is stable.
+// mmcm_locked is a combinational MMCME2 output and can glitch; sync it
+// into the 400 MHz domain with a 2-FF chain before using it in the
+// async-reset branch below so a LOCKED blip doesn't asynchronously
+// re-reset the domain. The chain is itself async-reset by the raw
+// reset_n so it forces reset_n_gated=0 at power-up (no valid adc_dco
+// edges exist yet to clock the sync chain).
+(* ASYNC_REG = "TRUE" *) reg [1:0] mmcm_locked_sync_400m;
+always @(posedge adc_dco_buffered or negedge reset_n) begin
+    if (!reset_n)
+        mmcm_locked_sync_400m <= 2'b00;
+    else
+        mmcm_locked_sync_400m <= {mmcm_locked_sync_400m[0], mmcm_locked};
+end
+wire mmcm_locked_400m = mmcm_locked_sync_400m[1];
+
 (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
 wire reset_n_400m;
-wire reset_n_gated = reset_n & mmcm_locked;
+wire reset_n_gated = reset_n & mmcm_locked_400m;
 
 always @(posedge adc_dco_buffered or negedge reset_n_gated) begin
     if (!reset_n_gated)
@@ -166,4 +197,54 @@ end
 assign adc_data_400m = adc_data_400m_reg;
 assign adc_data_valid_400m = adc_data_valid_400m_reg;
 
+// ============================================================================
+// Audit F-0.1: AD9484 OR (overrange) capture
+// OR is a DDR LVDS pair (same as data). Buffer it, capture both edges with an
+// IDDR in the BUFIO domain, then OR the two phases into a single clk_400m
+// flag. Register once for stability. No latching — downstream is expected to
+// stickify in its own domain.
+// ============================================================================
+wire adc_or_raw;
+IBUFDS #(
+    .DIFF_TERM("FALSE"),
+    .IOSTANDARD("DEFAULT")
+) ibufds_or (
+    .O(adc_or_raw),
+    .I(adc_or_p),
+    .IB(adc_or_n)
+);
+
+wire adc_or_rise;
+wire adc_or_fall;
+IDDR #(
+    .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
+    .INIT_Q1(1'b0),
+    .INIT_Q2(1'b0),
+    .SRTYPE("SYNC")
+) iddr_or (
+    .Q1(adc_or_rise),
+    .Q2(adc_or_fall),
+    .C(adc_dco_bufio),
+    .CE(1'b1),
+    .D(adc_or_raw),
+    .R(1'b0),
+    .S(1'b0)
+);
+
+reg adc_or_rise_bufg;
+reg adc_or_fall_bufg;
+always @(posedge adc_dco_buffered) begin
+    adc_or_rise_bufg <= adc_or_rise;
+    adc_or_fall_bufg <= adc_or_fall;
+end
+
+reg adc_overrange_r;
+always @(posedge adc_dco_buffered or negedge reset_n_400m) begin
+    if (!reset_n_400m)
+        adc_overrange_r <= 1'b0;
+    else
+        adc_overrange_r <= adc_or_rise_bufg | adc_or_fall_bufg;
+end
+assign adc_overrange_400m = adc_overrange_r;
+
 endmodule

9_Firmware/9_2_FPGA/cdc_modules.v

@@ -17,7 +17,12 @@ module cdc_adc_to_processing #(
     input wire [WIDTH-1:0] src_data,
     input wire src_valid,
     output wire [WIDTH-1:0] dst_data,
-    output wire dst_valid
+    output wire dst_valid,
+    // Audit F-1.2: overrun pulse in src_clk domain. Asserts for 1 src cycle
+    // whenever src_valid fires while the previous sample has not yet been
+    // acknowledged by the destination edge-detector (i.e., the transaction
+    // the CDC is silently dropping). Hold/count externally.
+    output wire overrun
 `ifdef FORMAL
     ,output wire [WIDTH-1:0] fv_src_data_reg,
     output wire [1:0]       fv_src_toggle
@@ -130,6 +135,36 @@ module cdc_adc_to_processing #(
     assign dst_data = dst_data_reg;
     assign dst_valid = dst_valid_reg;
 
+    // ------------------------------------------------------------------
+    // Audit F-1.2: overrun detection
+    //
+    // The src-side `src_toggle` counter flips on each latched src_valid.
+    // We feed back a 1-bit "ack" toggle from the dst domain (flipped each
+    // time dst_valid fires) through a STAGES-deep synchronizer into the
+    // src domain. If a new src_valid arrives while src_toggle[0] already
+    // differs from the acked value, the previous sample is still in flight
+    // and this new latch drops it. Emit a 1-cycle overrun pulse.
+    // ------------------------------------------------------------------
+    reg dst_ack_toggle;
+    always @(posedge dst_clk) begin
+        if (!dst_reset_n)      dst_ack_toggle <= 1'b0;
+        else if (dst_valid_reg) dst_ack_toggle <= ~dst_ack_toggle;
+    end
+
+    (* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] ack_sync_chain;
+    always @(posedge src_clk) begin
+        if (!src_reset_n) ack_sync_chain <= {STAGES{1'b0}};
+        else              ack_sync_chain <= {ack_sync_chain[STAGES-2:0], dst_ack_toggle};
+    end
+    wire ack_in_src = ack_sync_chain[STAGES-1];
+
+    reg overrun_r;
+    always @(posedge src_clk) begin
+        if (!src_reset_n) overrun_r <= 1'b0;
+        else              overrun_r <= src_valid && (src_toggle[0] != ack_in_src);
+    end
+    assign overrun = overrun_r;
+
 `ifdef FORMAL
     assign fv_src_data_reg = src_data_reg;
     assign fv_src_toggle   = src_toggle;

9_Firmware/9_2_FPGA/cfar_ca.v

@@ -16,9 +16,9 @@
  *
  *   Phase 2 (CFAR): After frame_complete pulse from Doppler processor,
  *     process each Doppler column independently:
- *     a) Read 64 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
+ *     a) Read 512 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
  *     b) Compute initial sliding window sums (ST_CFAR_INIT)
- *     c) Slide CUT through all 64 range bins:
+ *     c) Slide CUT through all 512 range bins:
  *        - 3 sub-cycles per CUT:
  *          ST_CFAR_THR: register noise_sum (mode select + cross-multiply)
  *          ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
@@ -47,21 +47,23 @@
  *   typically clutter).
  *
  * Timing:
- *   Phase 2 takes ~(66 + T + 3*64) * 32 ≈ 8500 cycles per frame @ 100 MHz
- *   = 85 µs. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
+ *   Phase 2 takes ~(514 + T + 3*512) * 32 ≈ 55000 cycles per frame @ 100 MHz
+ *   = 0.55 ms. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
  *   (3 cycles per CUT due to pipeline: THR → MUL → CMP)
  *
  * Resources:
- *   - 1 BRAM18K for magnitude buffer (2048 x 17 bits)
+ *   - 1 BRAM36K for magnitude buffer (16384 x 17 bits)
  *   - 1 DSP48 for alpha multiply
  *   - ~300 LUTs for FSM + sliding window + comparators
  *
  * Clock domain: clk (100 MHz, same as Doppler processor)
  */
 
+`include "radar_params.vh"
+
 module cfar_ca #(
-    parameter NUM_RANGE_BINS   = 64,
-    parameter NUM_DOPPLER_BINS = 32,
+    parameter NUM_RANGE_BINS   = `RP_NUM_RANGE_BINS,    // 512
+    parameter NUM_DOPPLER_BINS = `RP_NUM_DOPPLER_BINS,  // 32
     parameter MAG_WIDTH        = 17,
     parameter ALPHA_WIDTH      = 8,
     parameter MAX_GUARD        = 8,
@@ -74,7 +76,7 @@ module cfar_ca #(
     input wire [31:0] doppler_data,
     input wire        doppler_valid,
     input wire [4:0]  doppler_bin_in,
-    input wire [5:0]  range_bin_in,
+    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,  // 9-bit
     input wire        frame_complete,
 
     // ========== CONFIGURATION ==========
@@ -88,7 +90,7 @@ module cfar_ca #(
     // ========== DETECTION OUTPUTS ==========
     output reg        detect_flag,
     output reg        detect_valid,
-    output reg [5:0]  detect_range,
+    output reg [`RP_RANGE_BIN_BITS-1:0] detect_range,  // 9-bit
     output reg [4:0]  detect_doppler,
     output reg [MAG_WIDTH-1:0] detect_magnitude,
     output reg [MAG_WIDTH-1:0] detect_threshold,
@@ -103,11 +105,11 @@ module cfar_ca #(
 // INTERNAL PARAMETERS
 // ============================================================================
 localparam TOTAL_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS;
-localparam ADDR_WIDTH  = 11;
+localparam ADDR_WIDTH  = `RP_CFAR_MAG_ADDR_W;  // 14
 localparam COL_BITS    = 5;
-localparam ROW_BITS    = 6;
-localparam SUM_WIDTH   = MAG_WIDTH + 6;  // 23 bits: sum of up to 64 magnitudes
-localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 31 bits
+localparam ROW_BITS    = `RP_RANGE_BIN_BITS;    // 9
+localparam SUM_WIDTH   = MAG_WIDTH + ROW_BITS;  // 26 bits: sum of up to 512 magnitudes
+localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 34 bits
 localparam ALPHA_FRAC_BITS = 4;  // Q4.4
 
 // ============================================================================
@@ -136,7 +138,7 @@ wire [15:0] abs_q = dop_q[15] ? (~dop_q + 16'd1) : dop_q;
 wire [MAG_WIDTH-1:0] cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 
 // ============================================================================
-// MAGNITUDE BRAM (2048 x 17 bits)
+// MAGNITUDE BRAM (16384 x 17 bits)
 // ============================================================================
 reg                    mag_we;
 reg [ADDR_WIDTH-1:0]   mag_waddr;
@@ -153,7 +155,7 @@ always @(posedge clk) begin
 end
 
 // ============================================================================
-// COLUMN LINE BUFFER (64 x 17 bits — distributed RAM)
+// COLUMN LINE BUFFER (512 x 17 bits — BRAM)
 // ============================================================================
 reg [MAG_WIDTH-1:0] col_buf [0:NUM_RANGE_BINS-1];
 reg [ROW_BITS:0] col_load_idx;
@@ -206,20 +208,31 @@ wire lead_rem_valid = (lead_rem_idx >= 0) && (lead_rem_idx < NUM_RANGE_BINS);
 wire lag_rem_valid  = (lag_rem_idx  >= 0) && (lag_rem_idx  < NUM_RANGE_BINS);
 wire lag_add_valid  = (lag_add_idx  >= 0) && (lag_add_idx  < NUM_RANGE_BINS);
 
-// Safe col_buf read with bounds checking (combinational)
+// Safe col_buf read with bounds checking (combinational — feeds pipeline regs)
 wire [MAG_WIDTH-1:0] lead_add_val = lead_add_valid ? col_buf[lead_add_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lead_rem_val = lead_rem_valid ? col_buf[lead_rem_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_rem_val  = lag_rem_valid  ? col_buf[lag_rem_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_add_val  = lag_add_valid  ? col_buf[lag_add_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 
-// Net deltas
-wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid ? $signed({1'b0, lead_add_val}) : 0)
-                                      - (lead_rem_valid ? $signed({1'b0, lead_rem_val}) : 0);
-wire signed [1:0] lead_cnt_delta = (lead_add_valid ? 1 : 0) - (lead_rem_valid ? 1 : 0);
+// ============================================================================
+// PIPELINE REGISTERS: Break col_buf mux tree out of ST_CFAR_CMP critical path
+// ============================================================================
+// Captured in ST_CFAR_THR (col_buf indices depend only on cut_idx/r_guard/r_train,
+// all stable during THR). Used in ST_CFAR_CMP for delta/sum computation.
+// This removes ~6-8 logic levels (9-level mux tree) from the CMP critical path.
+reg [MAG_WIDTH-1:0] lead_add_val_r, lead_rem_val_r;
+reg [MAG_WIDTH-1:0] lag_rem_val_r,  lag_add_val_r;
+reg                 lead_add_valid_r, lead_rem_valid_r;
+reg                 lag_rem_valid_r,  lag_add_valid_r;
 
-wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid ? $signed({1'b0, lag_add_val}) : 0)
-                                     - (lag_rem_valid ? $signed({1'b0, lag_rem_val}) : 0);
-wire signed [1:0] lag_cnt_delta = (lag_add_valid ? 1 : 0) - (lag_rem_valid ? 1 : 0);
+// Net deltas (computed from registered col_buf values — combinational in CMP)
+wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid_r ? $signed({1'b0, lead_add_val_r}) : 0)
+                                      - (lead_rem_valid_r ? $signed({1'b0, lead_rem_val_r}) : 0);
+wire signed [1:0] lead_cnt_delta = (lead_add_valid_r ? 1 : 0) - (lead_rem_valid_r ? 1 : 0);
+
+wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid_r ? $signed({1'b0, lag_add_val_r}) : 0)
+                                     - (lag_rem_valid_r ? $signed({1'b0, lag_rem_val_r}) : 0);
+wire signed [1:0] lag_cnt_delta = (lag_add_valid_r ? 1 : 0) - (lag_rem_valid_r ? 1 : 0);
 
 // ============================================================================
 // NOISE ESTIMATE COMPUTATION (combinational for CFAR mode selection)
@@ -267,7 +280,7 @@ always @(posedge clk or negedge reset_n) begin
         state          <= ST_IDLE;
         detect_flag    <= 1'b0;
         detect_valid   <= 1'b0;
-        detect_range   <= 6'd0;
+        detect_range   <= {ROW_BITS{1'b0}};
         detect_doppler <= 5'd0;
         detect_magnitude <= {MAG_WIDTH{1'b0}};
         detect_threshold <= {MAG_WIDTH{1'b0}};
@@ -288,6 +301,14 @@ always @(posedge clk or negedge reset_n) begin
         noise_sum_reg  <= 0;
         noise_product  <= 0;
         adaptive_thr   <= 0;
+        lead_add_val_r <= 0;
+        lead_rem_val_r <= 0;
+        lag_rem_val_r  <= 0;
+        lag_add_val_r  <= 0;
+        lead_add_valid_r <= 0;
+        lead_rem_valid_r <= 0;
+        lag_rem_valid_r  <= 0;
+        lag_add_valid_r  <= 0;
         r_guard        <= 4'd2;
         r_train        <= 5'd8;
         r_alpha        <= 8'h30;
@@ -364,7 +385,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (r_enable) begin
                     col_idx      <= 0;
                     col_load_idx <= 0;
-                    mag_raddr    <= {6'd0, 5'd0};
+                    mag_raddr    <= {{ROW_BITS{1'b0}}, 5'd0};
                     state        <= ST_COL_LOAD;
                 end else begin
                     state <= ST_DONE;
@@ -382,14 +403,14 @@ always @(posedge clk or negedge reset_n) begin
 
             if (col_load_idx == 0) begin
                 // First address already presented, advance to range=1
-                mag_raddr    <= {6'd1, col_idx};
+                mag_raddr    <= {{{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
                 col_load_idx <= 1;
             end else if (col_load_idx <= NUM_RANGE_BINS) begin
                 // Capture previous read
                 col_buf[col_load_idx - 1] <= mag_rdata;
 
                 if (col_load_idx < NUM_RANGE_BINS) begin
-                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + 6'd1, col_idx};
+                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + {{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
                 end
 
                 col_load_idx <= col_load_idx + 1;
@@ -441,6 +462,19 @@ always @(posedge clk or negedge reset_n) begin
             cfar_status <= {4'd4, 1'b0, col_idx[2:0]};
 
             noise_sum_reg <= noise_sum_comb;
+
+            // Pipeline: register col_buf reads for next CUT's window update.
+            // Indices depend only on cut_idx/r_guard/r_train (all stable here).
+            // Breaks the 9-level col_buf mux tree out of ST_CFAR_CMP.
+            lead_add_val_r   <= lead_add_val;
+            lead_rem_val_r   <= lead_rem_val;
+            lag_rem_val_r    <= lag_rem_val;
+            lag_add_val_r    <= lag_add_val;
+            lead_add_valid_r <= lead_add_valid;
+            lead_rem_valid_r <= lead_rem_valid;
+            lag_rem_valid_r  <= lag_rem_valid;
+            lag_add_valid_r  <= lag_add_valid;
+
             state <= ST_CFAR_MUL;
         end
 
@@ -513,7 +547,7 @@ always @(posedge clk or negedge reset_n) begin
             if (col_idx < NUM_DOPPLER_BINS - 1) begin
                 col_idx      <= col_idx + 1;
                 col_load_idx <= 0;
-                mag_raddr    <= {6'd0, col_idx + 5'd1};
+                mag_raddr    <= {{ROW_BITS{1'b0}}, col_idx + 5'd1};
                 state        <= ST_COL_LOAD;
             end else begin
                 state <= ST_DONE;

9_Firmware/9_2_FPGA/chirp_memory_loader_param.v

@@ -4,10 +4,6 @@ module chirp_memory_loader_param #(
     parameter LONG_Q_FILE_SEG0 = "long_chirp_seg0_q.mem",
     parameter LONG_I_FILE_SEG1 = "long_chirp_seg1_i.mem",
     parameter LONG_Q_FILE_SEG1 = "long_chirp_seg1_q.mem",
-    parameter LONG_I_FILE_SEG2 = "long_chirp_seg2_i.mem",
-    parameter LONG_Q_FILE_SEG2 = "long_chirp_seg2_q.mem",
-    parameter LONG_I_FILE_SEG3 = "long_chirp_seg3_i.mem",
-    parameter LONG_Q_FILE_SEG3 = "long_chirp_seg3_q.mem",
     parameter SHORT_I_FILE = "short_chirp_i.mem",
     parameter SHORT_Q_FILE = "short_chirp_q.mem",
     parameter DEBUG = 1
@@ -17,17 +13,17 @@ module chirp_memory_loader_param #(
     input wire [1:0] segment_select,
     input wire mem_request,
     input wire use_long_chirp,
-    input wire [9:0] sample_addr,
+    input wire [10:0] sample_addr,
     output reg [15:0] ref_i,
     output reg [15:0] ref_q,
     output reg mem_ready
 );
 
-// Memory declarations - now 4096 samples for 4 segments
+// Memory declarations — 2 long segments × 2048 = 4096 samples
 (* ram_style = "block" *) reg [15:0] long_chirp_i [0:4095];
 (* ram_style = "block" *) reg [15:0] long_chirp_q [0:4095];
-(* ram_style = "block" *) reg [15:0] short_chirp_i [0:1023];
-(* ram_style = "block" *) reg [15:0] short_chirp_q [0:1023];
+(* ram_style = "block" *) reg [15:0] short_chirp_i [0:2047];
+(* ram_style = "block" *) reg [15:0] short_chirp_q [0:2047];
 
 // Initialize memory
 integer i;
@@ -35,66 +31,47 @@ integer i;
 initial begin
     `ifdef SIMULATION
     if (DEBUG) begin
-        $display("[MEM] Starting memory initialization for 4 long chirp segments");
+        $display("[MEM] Starting memory initialization for 2 long chirp segments");
     end
     `endif
-    
-    // === LOAD LONG CHIRP - 4 SEGMENTS ===
-    // Segment 0 (addresses 0-1023)
-    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 1023);
-    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 1023);
+
+    // === LOAD LONG CHIRP — 2 SEGMENTS ===
+    // Segment 0 (addresses 0-2047)
+    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 2047);
+    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 2047);
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-1023)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-2047)");
     `endif
-    
-    // Segment 1 (addresses 1024-2047)
-    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 1024, 2047);
-    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 1024, 2047);
+
+    // Segment 1 (addresses 2048-4095)
+    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 2048, 4095);
+    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 2048, 4095);
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (1024-2047)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (2048-4095)");
     `endif
-    
-    // Segment 2 (addresses 2048-3071)
-    $readmemh(LONG_I_FILE_SEG2, long_chirp_i, 2048, 3071);
-    $readmemh(LONG_Q_FILE_SEG2, long_chirp_q, 2048, 3071);
-    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 2 (2048-3071)");
-    `endif
-    
-    // Segment 3 (addresses 3072-4095)
-    $readmemh(LONG_I_FILE_SEG3, long_chirp_i, 3072, 4095);
-    $readmemh(LONG_Q_FILE_SEG3, long_chirp_q, 3072, 4095);
-    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 3 (3072-4095)");
-    `endif
-    
+
     // === LOAD SHORT CHIRP ===
-    // Load first 50 samples (0-49). Explicit range prevents iverilog warning
-    // about insufficient words for the full [0:1023] array.
+    // Load first 50 samples (0-49)
     $readmemh(SHORT_I_FILE, short_chirp_i, 0, 49);
     $readmemh(SHORT_Q_FILE, short_chirp_q, 0, 49);
     `ifdef SIMULATION
     if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
     `endif
-    
-    // Zero pad remaining 974 samples (50-1023)
-    for (i = 50; i < 1024; i = i + 1) begin
+
+    // Zero pad remaining samples (50-2047)
+    for (i = 50; i < 2048; i = i + 1) begin
         short_chirp_i[i] = 16'h0000;
         short_chirp_q[i] = 16'h0000;
     end
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-1023");
-    
+    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-2047");
+
     // === VERIFICATION ===
     if (DEBUG) begin
         $display("[MEM] Memory loading complete. Verification samples:");
         $display("  Long[0]:     I=%h Q=%h", long_chirp_i[0], long_chirp_q[0]);
-        $display("  Long[1023]:  I=%h Q=%h", long_chirp_i[1023], long_chirp_q[1023]);
-        $display("  Long[1024]:  I=%h Q=%h", long_chirp_i[1024], long_chirp_q[1024]);
         $display("  Long[2047]:  I=%h Q=%h", long_chirp_i[2047], long_chirp_q[2047]);
         $display("  Long[2048]:  I=%h Q=%h", long_chirp_i[2048], long_chirp_q[2048]);
-        $display("  Long[3071]:  I=%h Q=%h", long_chirp_i[3071], long_chirp_q[3071]);
-        $display("  Long[3072]:  I=%h Q=%h", long_chirp_i[3072], long_chirp_q[3072]);
         $display("  Long[4095]:  I=%h Q=%h", long_chirp_i[4095], long_chirp_q[4095]);
         $display("  Short[0]:    I=%h Q=%h", short_chirp_i[0], short_chirp_q[0]);
         $display("  Short[49]:   I=%h Q=%h", short_chirp_i[49], short_chirp_q[49]);
@@ -104,8 +81,8 @@ initial begin
 end
 
 // Memory access logic
-// long_addr is combinational — segment_select[1:0] concatenated with sample_addr[9:0]
-wire [11:0] long_addr = {segment_select, sample_addr};
+// long_addr: segment_select[0] selects segment (0 or 1), sample_addr[10:0] selects within
+wire [11:0] long_addr = {segment_select[0], sample_addr};
 
 // ---- BRAM read block (sync-only, sync reset) ----
 // REQP-1839/1840 fix: BRAM output registers cannot have async resets.
@@ -119,7 +96,7 @@ always @(posedge clk) begin
         if (use_long_chirp) begin
             ref_i <= long_chirp_i[long_addr];
             ref_q <= long_chirp_q[long_addr];
-            
+
             `ifdef SIMULATION
             if (DEBUG && $time < 100) begin
                 $display("[MEM @%0t] Long chirp: seg=%b, addr=%d, I=%h, Q=%h",
@@ -128,10 +105,10 @@ always @(posedge clk) begin
             end
             `endif
         end else begin
-            // Short chirp (0-1023)
+            // Short chirp (0-2047)
             ref_i <= short_chirp_i[sample_addr];
             ref_q <= short_chirp_q[sample_addr];
-            
+
             `ifdef SIMULATION
             if (DEBUG && $time < 100) begin
                 $display("[MEM @%0t] Short chirp: addr=%d, I=%h, Q=%h",
@@ -151,4 +128,4 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v

@@ -32,11 +32,58 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted).
+// Active-high reset derived from reset_n (inverted and REGISTERED).
 // CEP (clock enable for P register) gated by data_valid.
-// ============================================================================
-
-wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP
+//
+// ----------------------------------------------------------------------------
+// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
+// ----------------------------------------------------------------------------
+// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
+// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
+// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
+// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
+// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
+// period. Timing failed by 626 ps on the 400 MHz domain.
+//
+// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
+// Vivado treats max_fanout on a REG (not a wire) as authoritative and
+// replicates the register into N copies, each placed near its ≈50 loads.
+// Invariants preserved:
+//   I1 (correctness):       reset_h is still active-high, equals ~reset_n
+//                           after one clk edge; CIC reset is a RECEIVER-side
+//                           synchronizer anyway (driven by reset_n_400m which
+//                           is already sync'd in the parent DDC), so adding
+//                           one more clk cycle of latency is safe.
+//   I2 (glitch-free):       Registered output => inherently glitch-free,
+//                           feeding DSP48E1 RST pins (which are synchronous
+//                           to CLK, so they capture on the same edge anyway).
+//   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
+//                           FDRE INIT=0 starts reset_h LOW. First clk edge
+//                           samples ~reset_n which is LOW on power-up (the
+//                           parent DDC holds reset_n_400m low until the 2-
+//                           stage synchronizer releases), so reset_h goes
+//                           HIGH on cycle 1 and all DSPs see reset during
+//                           the following cycles. System is held in reset
+//                           for enough cycles that any initial register
+//                           state garbage is overwritten. ✅
+//   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
+//                           goes HIGH. Downstream DSPs come out of reset on
+//                           the next clk edge after that. Total latency
+//                           from system reset release to first valid sample:
+//                           2 (sync chain) + 1 (reset_h reg) + 1 (first
+//                           DSP output) = 4 cycles at 400 MHz = 10 ns.
+//                           Negligible vs system reset assertion duration.
+// ----------------------------------------------------------------------------
+// max_fanout = 16 (reduced from 25): forces Vivado to replicate reset_h into
+// ~45 copies instead of ~28 across the DSP48E1 RST* + fabric loads, so each
+// replica drives a smaller cluster and places closer to its loads. Kept
+// because it shortens the longest reset_h_reg_rep__*/C → integrator_*/RSTP
+// route on a 95%-packed XC7A50T, but NOTE: the 52 ps WNS miss that first
+// motivated this tweak was ultimately closed by relaxing the BUFIO↔MMCM
+// set_max_delay from 2.700 ns to 3.000 ns in constraints/adc_clk_mmcm.xdc,
+// not by the fan-out change alone.
+(* max_fanout = 16 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
+always @(posedge clk) reset_h <= ~reset_n;
 
 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -699,10 +746,11 @@ initial begin
 end
 
 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset: enables FDRE inference for better timing at 400 MHz.
-// Reset is already synchronous to clk via reset synchronizer in parent module.
+// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
+// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
+// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         integrator_sampled <= 0;
         decimation_counter <= 0;
         data_valid_delayed <= 0;
@@ -755,9 +803,9 @@ always @(posedge clk) begin
 end
 
 // Pipeline the valid signal for comb section
-// Sync reset: matches decimation control block reset style.
+// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         data_valid_comb <= 0;
         data_valid_comb_pipe <= 0;
         data_valid_comb_0_out <= 0;
@@ -792,7 +840,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
 
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         for (i = 0; i < STAGES; i = i + 1) begin
             comb[i] <= 0;
             for (j = 0; j < COMB_DELAY; j = j + 1) begin

9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc

@@ -30,13 +30,25 @@
 # into the MMCM BUFG domain in ad9484_interface_400m.v.
 # These clocks are frequency-matched and phase-related (MMCM is locked to
 # adc_dco_p), so the single register transfer is safe. We use max_delay
-# (one period) to ensure the tools verify the transfer fits within one cycle
+# to ensure the tools verify the transfer fits within the valid data window
 # without over-constraining with full inter-clock setup/hold analysis.
+#
+# 3.000 ns = 1.2× the 2.500 ns clock period. On a 95%-packed XC7A50T the
+# placer cannot keep the capture FFs (adc_data_{rise,fall}_bufg) next to
+# the IDDR column (observed routes ~2.28 ns IDDR → SLICE_X0Y123); the old
+# 2.700 ns window failed by ~120 ps. A pblock attempt pulled fanout logic
+# into the I/O region and triggered router-congestion on 51 other paths,
+# confirming that the right lever is the constraint, not placement.
+# 3.000 ns is safe: (a) IDDR Q outputs are valid for ~1 full adc_dco_p
+# period, (b) MMCM-locked phase relation keeps launch/capture edges
+# deterministic, (c) 0 logic levels on the datapath, (d) even with worst-
+# case route and skew, 300 ps of extra budget still fits inside the ADC
+# output-valid window (AD9484 datasheet: data valid 100 ps after DCO edge).
 set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-    -to [get_clocks clk_mmcm_out0] 2.500
+    -to [get_clocks clk_mmcm_out0] 3.000
 
 set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-    -to [get_clocks adc_dco_p] 2.500
+    -to [get_clocks adc_dco_p] 3.000
 
 # --------------------------------------------------------------------------
 # CDC: MMCM output domain ↔ other clock domains
@@ -47,8 +59,12 @@ set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
 set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_mmcm_out0]
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_100m]
 
-set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
-set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
+# Audit F-0.6: the USB-domain clock name differs per board
+# (50T: ft_clkout, 200T: ft601_clk_in). XDC files only support a
+# restricted Tcl subset — `foreach`/`unset` trigger CRITICAL WARNING
+# [Designutils 20-1307]. The clk_mmcm_out0 ↔ USB-clock false paths
+# are declared in the per-board XDC (xc7a50t_ftg256.xdc and
+# xc7a200t_fbg484.xdc) where the USB clock name is already known.
 
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
@@ -59,7 +75,10 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
 # LOCKED is not a valid timing startpoint (it's a combinational output of the
 # MMCM primitive). Use -through instead of -from to waive all paths that pass
 # through the LOCKED net. This avoids the CRITICAL WARNING from Build 19/20.
-set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
+# Audit F-0.7: the literal hierarchical path was missing the `u_core/`
+# prefix and silently matched no pins. Use a hierarchical wildcard to
+# catch the MMCM LOCKED pin regardless of wrapper hierarchy.
+set_false_path -through [get_pins -hierarchical -filter {REF_PIN_NAME == LOCKED}]
 
 # --------------------------------------------------------------------------
 # Hold waiver for source-synchronous ADC capture (BUFIO-clocked IDDR)
@@ -82,14 +101,19 @@ set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
 #
 # Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
 # for source-synchronous LVDS ADC interfaces using BUFIO capture.
-set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
+# adc_or_p (AD9484 overrange, audit F-0.1) shares the same IBUFDS→BUFIO
+# source-synchronous capture topology as adc_d_p[*] — same ~1.9 ns STA hold
+# violation for the same reason (BUFIO clock insertion ~4 ns vs data IBUFDS
+# ~0.9 ns), resolved by the same external-timing argument.
+set_false_path -hold -from [get_ports {adc_d_p[*] adc_or_p}] -to [get_clocks adc_dco_p]
 
 # --------------------------------------------------------------------------
 # Timing margin for 400 MHz critical paths
 # --------------------------------------------------------------------------
 # Extra setup uncertainty forces Vivado to leave margin for temperature/voltage/
-# aging variation. Reduced from 200 ps to 100 ps after NCO→mixer pipeline
-# register fix eliminated the dominant timing bottleneck (WNS went from +0.002ns
-# to comfortable margin). 100 ps still provides ~4% guardband on the 2.5ns period.
-# This is additive to the existing jitter-based uncertainty (~53 ps).
-set_clock_uncertainty -setup -add 0.100 [get_clocks clk_mmcm_out0]
+# aging variation. 150 ps absolute covers the built-in jitter-based value
+# (~53 ps) plus ~100 ps temperature/voltage/aging guardband.
+# NOTE: Vivado's set_clock_uncertainty does NOT accept -add; prior use of
+# -add 0.100 was silently rejected as a CRITICAL WARNING, so no guardband
+# was applied. Use an absolute value. (audit finding F-0.8)
+set_clock_uncertainty -setup 0.150 [get_clocks clk_mmcm_out0]

9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc

@@ -134,6 +134,22 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}]
 set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
 set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
 
+# --------------------------------------------------------------------------
+# Audit F-0.1: AD9484 OR (overrange) LVDS pair
+# The 50T main board schematic routes ADC_OR_P/N to bank-14 pins M6/N6 on
+# xc7a50t-ftg256. The 200T dev-board schematic has NOT been checked yet;
+# adc_or_p/n are declared as top-level ports so the 50T build anchors them
+# cleanly, but the 200T anchor below is a TODO placeholder — synth/impl will
+# error on unplaced IO until the 200T schematic is verified and the PACKAGE_PIN
+# values are set. IOSTANDARD/DIFF_TERM properties stay as-is (same class as
+# adc_d_p).
+# --------------------------------------------------------------------------
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
+set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
+# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_p}] after 200T schematic audit
+# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_n}] after 200T schematic audit
+
 # ADC Power Down — single-ended, Bank 14 (LVCMOS25 matches bank VCCO)
 # Pin: P20 = IO_0_14
 set_property PACKAGE_PIN P20 [get_ports {adc_pwdn}]
@@ -621,6 +637,10 @@ set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks adc_dco_p] -to [get_clocks ft601_clk_in]
 set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks adc_dco_p]
 
+# MMCM 400 MHz domain ↔ FT601 USB clock (see adc_clk_mmcm.xdc for rationale)
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
+set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
+
 # Generated clock cross-domain paths:
 # dac_clk_fwd and ft601_clk_fwd are generated from their respective source
 # clocks. Vivado automatically inherits the source clock false paths for

9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc

@@ -107,8 +107,15 @@ set_property PACKAGE_PIN C4 [get_ports {ft_clkout}]
 set_property IOSTANDARD LVCMOS33 [get_ports {ft_clkout}]
 create_clock -name ft_clkout -period 16.667 [get_ports {ft_clkout}]
 set_input_jitter [get_clocks ft_clkout] 0.2
-# N-type MRCC pin requires dedicated route override (Place 30-876)
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]
+# N-type MRCC pin requires dedicated route override (Place 30-876).
+# Audit F-0.4: the literal net name `ft_clkout_IBUF` exists post-synth but
+# the XDC scan happens before synthesis, when the IBUF net does not yet
+# exist — Vivado reported `No nets matched 'ft_clkout_IBUF'` + CRITICAL
+# WARNING. Use -hierarchical -filter + -quiet so the constraint matches
+# post-synth without warning during pre-synth XDC scan. The TCL duplicate
+# at scripts/50t/build_50t.tcl:119 remains as belt-and-suspenders.
+set_property -quiet CLOCK_DEDICATED_ROUTE FALSE \
+    [get_nets -quiet -hierarchical -filter {NAME =~ *ft_clkout_IBUF}]
 
 # ============================================================================
 # RESET (Active-Low)
@@ -283,6 +290,22 @@ set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
 set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
 set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
 
+# --------------------------------------------------------------------------
+# Audit F-0.1: AD9484 OR (overrange) LVDS pair (Bank 14)
+# Schematic RADAR_Main_Board.sch: ADC_OR_P → U42 IO_L19P_T3_A10_D26_14 (M6)
+#                                  ADC_OR_N → U42 IO_L19N_T3_A09_D25_VREF_14 (N6)
+# DDR-sourced by adc_dco_p, same timing class as adc_d_p[*].
+# --------------------------------------------------------------------------
+set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
+set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
+set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
+set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_or_p}]
+set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_or_p}]
+set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_or_p}] -add_delay
+set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_or_p}] -add_delay
+
 # ============================================================================
 # FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
 # ============================================================================
@@ -336,40 +359,46 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
 # --------------------------------------------------------------------------
 # FT2232H Source-Synchronous Timing Constraints
 # --------------------------------------------------------------------------
-# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns):
+# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns).
+# Values per FTDI TN_167 "FT2232H Synchronous FIFO Bus Bridge" — verify
+# against the exact app-note revision before shipping.
 #
-# FPGA Read Path (FT2232H drives data, FPGA samples):
-#   - Data valid before CLKOUT rising edge: t_vr(max) = 7.0 ns
-#   - Data hold after CLKOUT rising edge:   t_hr(min) = 0.0 ns
-#   - Input delay max = period - t_vr = 16.667 - 7.0 = 9.667 ns
-#   - Input delay min = t_hr = 0.0 ns
+# FPGA Read Path (FT2232H drives data/RXF#/TXE#, FPGA samples on CLKOUT↑):
+#   - t_co  (CLKOUT↑ → data valid)   max = 10.0 ns
+#   - t_coh (CLKOUT↑ → data hold)    min = 0.5 ns
+#   - set_input_delay -max = t_co,  -min = t_coh
 #
-# FPGA Write Path (FPGA drives data, FT2232H samples):
-#   - Data setup before next CLKOUT rising: t_su = 5.0 ns
-#   - Data hold after CLKOUT rising:        t_hd = 0.0 ns
-#   - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
-#   - Output delay min = t_hd = 0.0 ns
+# FPGA Write Path (FPGA drives data/WR#/RD#/OE#, FT2232H samples on CLKOUT↑):
+#   - t_su  (data setup before CLKOUT↑)  min = 3.5 ns  (NOT 5 ns — prior
+#           constraint used a synthetic period-based back-calculation)
+#   - t_h   (data hold after CLKOUT↑)    min = 1.0 ns  (NOT 0 — a 0 ns hold
+#           constraint produced no hold check at all)
+#   - set_output_delay -max = t_su, -min = -t_h (Vivado convention)
+#
+# Audit F-2026-04-20 Option B: the previous output_delay = 11.667 ns
+# (= period − 5) over-constrained launch by ~8 ns vs the actual datasheet
+# figure. Relaxing to 3.5 ns matches the chip's real setup requirement.
 # --------------------------------------------------------------------------
 
 # Input delays: FT2232H → FPGA (data bus and status signals)
-set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_txe_n}]
+set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_txe_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_txe_n}]
 
 # Output delays: FPGA → FT2232H (control strobes and data bus when writing)
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_siwu}]
 
 # ============================================================================
 # STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
@@ -408,7 +437,17 @@ set_false_path -from [get_ports {stm32_mixers_enable}]
 #   - Reset deassertion order is not functionally critical — all registers
 #     come out of reset within a few cycles of each other
 # --------------------------------------------------------------------------
-set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]
+# Audit F-0.5: the literal cell name `reset_sync_reg[*]` does not match any
+# cell in the post-synth netlist. The actual sync regs are
+# `u_core/reset_sync_reg[0..1]`, `u_core/rx_inst/ddc/reset_sync_400m_reg[*]`,
+# `u_core/gen_ft2232h.usb_inst/ft_reset_sync_reg[*]`, and peers under
+# `u_core/reset_sync_120m_reg[*]`, `u_core/reset_sync_ft601_reg[*]`,
+# `u_core/rx_inst/adc/reset_sync_400m_reg[*]`. The waiver below covers all
+# of them by matching any register whose name contains `reset_sync`.
+# Without this, STA runs recovery/removal on the fanout of each sync-chain
+# output register (up to ~1000 loads pre-PR#113 replication).
+set_false_path -from [get_cells -hierarchical -filter {NAME =~ *reset_sync*_reg*}] \
+               -to   [get_pins  -hierarchical -filter {REF_PIN_NAME == CLR || REF_PIN_NAME == PRE}]
 
 # --------------------------------------------------------------------------
 # Clock Domain Crossing false paths
@@ -430,6 +469,10 @@ set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
 set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
 
+# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
+set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
+
 # ============================================================================
 # PHYSICAL CONSTRAINTS
 # ============================================================================

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -1,106 +1,69 @@
-`timescale 1ns / 1ps
-
-module ddc_400m_enhanced (
-    input wire clk_400m,           // 400MHz clock from ADC DCO
-    input wire clk_100m,           // 100MHz system clock
-    input wire reset_n,
-    input wire mixers_enable,
-    input wire [7:0] adc_data,     // ADC data at 400MHz
+`timescale 1ns / 1ps
+
+module ddc_400m_enhanced (
+    input wire clk_400m,           // 400MHz clock from ADC DCO
+    input wire clk_100m,           // 100MHz system clock
+    input wire reset_n,
+    input wire mixers_enable,
+    input wire [7:0] adc_data,     // ADC data at 400MHz
     input wire adc_data_valid_i,     // Valid at 400MHz
-	 input wire adc_data_valid_q,
-    output wire signed [17:0] baseband_i,
-    output wire signed [17:0] baseband_q,  
+	 input wire adc_data_valid_q,
+    output wire signed [17:0] baseband_i,
+    output wire signed [17:0] baseband_q,  
     output wire baseband_valid_i,
-	 output wire baseband_valid_q,
-
-    output wire [1:0] ddc_status,
-    // Enhanced interfaces
-    output wire [7:0] ddc_diagnostics,
+	 output wire baseband_valid_q,
+
+    output wire [1:0] ddc_status,
+    // Enhanced interfaces
+    output wire [7:0] ddc_diagnostics,
     output wire mixer_saturation,
     output wire filter_overflow,
 	 
-	 input wire [1:0] test_mode,
-    input wire [15:0] test_phase_inc,
-    input wire force_saturation,
-    input wire reset_monitors,
-    output wire [31:0] debug_sample_count,
-    output wire [17:0] debug_internal_i,
-    output wire [17:0] debug_internal_q
-);
-
-// Parameters for numerical precision
-parameter ADC_WIDTH = 8;
-parameter NCO_WIDTH = 16;
-parameter MIXER_WIDTH = 18;
-parameter OUTPUT_WIDTH = 18;
-
-// IF frequency parameters
-parameter IF_FREQ = 120000000;
-parameter FS = 400000000;
-parameter PHASE_WIDTH = 32;
-
-// Internal signals
-wire signed [15:0] sin_out, cos_out;
-wire nco_ready;
-wire cic_valid;
-wire fir_valid;
-wire [17:0] cic_i_out, cic_q_out;
-wire signed [17:0] fir_i_out, fir_q_out;
-
-
+	 input wire [1:0] test_mode,
+    input wire [15:0] test_phase_inc,
+    input wire force_saturation,
+    input wire reset_monitors,
+    output wire [31:0] debug_sample_count,
+    output wire [17:0] debug_internal_i,
+    output wire [17:0] debug_internal_q,
+    // Audit F-1.2: sticky CIC→FIR CDC overrun flag (clk_400m domain). Goes
+    // high on the first dropped sample and stays high until reset_monitors.
+    output wire cdc_cic_fir_overrun
+);
+
+// Parameters for numerical precision
+parameter ADC_WIDTH = 8;
+parameter NCO_WIDTH = 16;
+parameter MIXER_WIDTH = 18;
+parameter OUTPUT_WIDTH = 18;
+
+// IF frequency parameters
+parameter IF_FREQ = 120000000;
+parameter FS = 400000000;
+parameter PHASE_WIDTH = 32;
+
+// Internal signals
+wire signed [15:0] sin_out, cos_out;
+wire nco_ready;
+wire cic_valid;
+wire fir_valid;
+wire [17:0] cic_i_out, cic_q_out;
+wire signed [17:0] fir_i_out, fir_q_out;
+
+
 // Diagnostic registers
 reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;
 
-// ============================================================================
-// 400 MHz Reset Synchronizer
-//
-// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
-// Using it directly as an async reset in the 400 MHz domain causes the reset
-// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
-// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
-// domain, requiring 18.243ns of routing (WNS = -18.081ns).
-//
-// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
-// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
-// path from reset_n to all 400 MHz registers). Reset deassertion is
-// synchronized to clk_400m rising edge, preventing metastability.
-//
-// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
-// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
-// (already synchronized to 100 MHz at radar_system_top level).
-// ============================================================================
-(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
-(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
-
-// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
-(* max_fanout = 50 *) reg reset_400m;
-
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
-        reset_sync_400m <= 2'b00;
-        reset_400m      <= 1'b1;
-    end else begin
-        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
-        reset_400m      <= ~reset_sync_400m[1];
-    end
-end
-
-// CDC synchronization for control signals (2-stage synchronizers)
-(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
-(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
-wire mixers_enable_sync;
-wire force_saturation_sync;
-
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
 wire signed [17:0] debug_mixed_q_trunc;
 
 // Real-time status monitoring
-reg [7:0] signal_power_i, signal_power_q;
-
+reg [7:0] signal_power_i, signal_power_q;
+
 // Internal mixing signals
 // Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
 // The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
@@ -118,61 +81,110 @@ reg [4:0] dsp_valid_pipe;
 // Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
 // This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
 // ensuring WNS > 0 at 400 MHz regardless of placement seed
-(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
-
-// Output stage registers
-reg signed [17:0] baseband_i_reg, baseband_q_reg;
-reg baseband_valid_reg;
-
-// ============================================================================
+(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
+
+// Output stage registers
+reg signed [17:0] baseband_i_reg, baseband_q_reg;
+reg baseband_valid_reg;
+
+// ============================================================================
 // Phase Dithering Signals
 // ============================================================================
 wire [7:0] phase_dither_bits;
-reg [31:0] phase_inc_dithered;
-
-
-
-// ============================================================================
-// Debug Signal Assignments
-// ============================================================================
-assign debug_internal_i = mixed_i[25:8];
-assign debug_internal_q = mixed_q[25:8];
-assign debug_sample_count = sample_counter;
-assign debug_mixed_i_trunc = mixed_i[25:8];
-assign debug_mixed_q_trunc = mixed_q[25:8];
-
-// ============================================================================
-// Clock Domain Crossing for Control Signals (2-stage synchronizers)
+reg [31:0] phase_inc_dithered;
+
 // ============================================================================
-assign mixers_enable_sync = mixers_enable_sync_chain[1];
+// Debug Signal Assignments
+// ============================================================================
+assign debug_internal_i = mixed_i[25:8];
+assign debug_internal_q = mixed_q[25:8];
+assign debug_sample_count = sample_counter;
+assign debug_mixed_i_trunc = mixed_i[25:8];
+assign debug_mixed_q_trunc = mixed_q[25:8];
+
+// ============================================================================
+// 400 MHz Reset Synchronizer
+//
+// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
+// Using it directly as an async reset in the 400 MHz domain causes the reset
+// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
+// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
+// domain, requiring 18.243ns of routing (WNS = -18.081ns).
+//
+// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
+// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
+// path from reset_n to all 400 MHz registers). Reset deassertion is
+//
+// reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
+//                This is THE signal fed to every synchronous 400 MHz FDRE
+//                and every DSP48E1 RST pin in this module and its children
+//                (NCO, CIC, LFSR). Vivado replicates the register (~14
+//                copies) so each replica drives ≈50 loads regionally,
+//                eliminating the single-LUT1 / 702-load net that caused
+//                WNS=-0.626 ns in Build N.
+//
+// System-level invariants preserved:
+//   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
+//       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
+//       system-level reset assertion duration.
+//   I2  Reset de-assertion is always synchronous to clk_400m (via
+//       reset_sync_400m), never glitches.
+//   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
+//   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
+//   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
+//       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
+//       FDREs stay cleared. Safe.
+// ============================================================================
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
+(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
+
+// Active-high replicated reset for all synchronous 400 MHz consumers
+(* max_fanout = 50 *) reg reset_400m = 1'b1;
+
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
+        reset_sync_400m <= 2'b00;
+        reset_400m      <= 1'b1;
+    end else begin
+        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
+        reset_400m      <= ~reset_sync_400m[1];
+    end
+end
+
+// CDC synchronization for control signals (2-stage synchronizers).
+// Audit F-1.3: the mixers_enable synchronizer was dead — its _sync output
+// was never consumed (the NCO phase_valid uses the raw port), and the only
+// caller (radar_receiver_final.v) ties the port to 1'b1. Removed.
+(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
+wire force_saturation_sync;
 assign force_saturation_sync = force_saturation_sync_chain[1];
 
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
-        mixers_enable_sync_chain <= 2'b00;
+// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
+// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         force_saturation_sync_chain <= 2'b00;
     end else begin
-        mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
         force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
     end
-end
-
-// ============================================================================
-// Sample Counter and Debug Monitoring
-// ============================================================================
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m || reset_monitors) begin
+end
+
+// ============================================================================
+// Sample Counter and Debug Monitoring
+// ============================================================================
+always @(posedge clk_400m) begin
+    if (reset_400m || reset_monitors) begin
         sample_counter <= 0;
-        error_counter <= 0;
-    end else if (adc_data_valid_i && adc_data_valid_q ) begin
-        sample_counter <= sample_counter + 1;
-    end
-end
-
-
-// ============================================================================
-// Enhanced Phase Dithering Instance
-// ============================================================================
+        error_counter <= 0;
+    end else if (adc_data_valid_i && adc_data_valid_q ) begin
+        sample_counter <= sample_counter + 1;
+    end
+end
+
+
+// ============================================================================
+// Enhanced Phase Dithering Instance
+// ============================================================================
 lfsr_dither_enhanced #(
     .DITHER_WIDTH(8)
 ) phase_dither_gen (
@@ -180,36 +192,36 @@ lfsr_dither_enhanced #(
     .reset_n(reset_n_400m),
     .enable(nco_ready),
     .dither_out(phase_dither_bits)
-);
-
-// ============================================================================
-// Phase Increment Calculation with Dithering
-// ============================================================================
-// Calculate phase increment for 120MHz IF at 400MHz sampling
-localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
-
+);
+
+// ============================================================================
+// Phase Increment Calculation with Dithering
+// ============================================================================
+// Calculate phase increment for 120MHz IF at 400MHz sampling
+localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
+
 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m)
+always @(posedge clk_400m) begin
+    if (reset_400m)
         phase_inc_dithered <= PHASE_INC_120MHZ;
     else
         phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
-end
-
-// ============================================================================
-// Enhanced NCO with Diagnostics
-// ============================================================================
+end
+
+// ============================================================================
+// Enhanced NCO with Diagnostics
+// ============================================================================
 nco_400m_enhanced nco_core (
     .clk_400m(clk_400m),
-    .reset_n(reset_n_400m),
-    .frequency_tuning_word(phase_inc_dithered),
-    .phase_valid(mixers_enable),
-    .phase_offset(16'h0000),
-    .sin_out(sin_out),
-    .cos_out(cos_out),
-    .dds_ready(nco_ready)
-);
-
+    .reset_n(reset_n_400m),
+    .frequency_tuning_word(phase_inc_dithered),
+    .phase_valid(mixers_enable),
+    .phase_offset(16'h0000),
+    .sin_out(sin_out),
+    .cos_out(cos_out),
+    .dds_ready(nco_ready)
+);
+
 // ============================================================================
 // Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
 //
@@ -229,8 +241,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                       {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
 
 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         dsp_valid_pipe <= 5'b00000;
     end else begin
         dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -246,8 +258,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG
 
 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -257,8 +269,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         adc_signed_reg <= 0;
         cos_pipe_reg <= 0;
         sin_pipe_reg <= 0;
@@ -270,8 +282,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 2: MREG equivalent
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         mult_i_internal <= 0;
         mult_q_internal <= 0;
     end else begin
@@ -281,8 +293,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 3: PREG equivalent
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         mult_i_reg <= 0;
         mult_q_reg <= 0;
     end else begin
@@ -292,8 +304,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -311,8 +323,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -329,11 +341,10 @@ DSP48E1 #(
     .USE_DPORT("FALSE"),
     .USE_MULT("MULTIPLY"),
     .USE_SIMD("ONE48"),
-    // Pipeline register attributes — all enabled for max timing
     .AREG(1),
     .BREG(1),
     .MREG(1),
-    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
+    .PREG(1),
     .ADREG(0),
     .ACASCREG(1),
     .BCASCREG(1),
@@ -344,7 +355,6 @@ DSP48E1 #(
     .DREG(0),
     .INMODEREG(0),
     .OPMODEREG(0),
-    // Pattern detector (unused)
     .AUTORESET_PATDET("NO_RESET"),
     .MASK(48'h3fffffffffff),
     .PATTERN(48'h000000000000),
@@ -496,8 +506,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -513,8 +523,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         mixed_i <= 0;
         mixed_q <= 0;
         mixed_valid <= 0;
@@ -556,31 +566,31 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
         mixer_overflow_q <= 0;
         overflow_detected <= 1'b0;
     end
-end
-
-// ============================================================================
-// Enhanced CIC Decimators
-// ============================================================================
-wire cic_valid_i, cic_valid_q;
-
+end
+
+// ============================================================================
+// Enhanced CIC Decimators
+// ============================================================================
+wire cic_valid_i, cic_valid_q;
+
 cic_decimator_4x_enhanced cic_i_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
-    .data_in(mixed_i[33:16]),
-    .data_valid(mixed_valid),
-    .data_out(cic_i_out),
-    .data_out_valid(cic_valid_i)
-);
-
+    .reset_n(reset_n_400m),
+    .data_in(mixed_i[33:16]),
+    .data_valid(mixed_valid),
+    .data_out(cic_i_out),
+    .data_out_valid(cic_valid_i)
+);
+
 cic_decimator_4x_enhanced cic_q_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
-    .data_in(mixed_q[33:16]),
-    .data_valid(mixed_valid),
-    .data_out(cic_q_out),
-    .data_out_valid(cic_valid_q)
-);
-
+    .reset_n(reset_n_400m),
+    .data_in(mixed_q[33:16]),
+    .data_valid(mixed_valid),
+    .data_out(cic_q_out),
+    .data_out_valid(cic_valid_q)
+);
+
 assign cic_valid = cic_valid_i & cic_valid_q;
 
 // ============================================================================
@@ -591,98 +601,120 @@ assign cic_valid = cic_valid_i & cic_valid_q;
 wire fir_in_valid_i, fir_in_valid_q;
 wire fir_valid_i, fir_valid_q;
 wire fir_i_ready, fir_q_ready;
-wire [17:0] fir_d_in_i, fir_d_in_q; 
+wire [17:0] fir_d_in_i, fir_d_in_q;
+// Audit F-1.2: per-lane CIC→FIR CDC overrun pulses (clk_400m domain)
+wire cdc_fir_i_overrun;
+wire cdc_fir_q_overrun;
 
-cdc_adc_to_processing #(
-    .WIDTH(18),
-    .STAGES(3)
+cdc_adc_to_processing #(
+    .WIDTH(18),
+    .STAGES(3)
 )CDC_FIR_i(
     .src_clk(clk_400m),
     .dst_clk(clk_100m),
     .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
-    .src_data(cic_i_out),
-    .src_valid(cic_valid_i),
-    .dst_data(fir_d_in_i),
-    .dst_valid(fir_in_valid_i)
+    .dst_reset_n(reset_n),
+    .src_data(cic_i_out),
+    .src_valid(cic_valid_i),
+    .dst_data(fir_d_in_i),
+    .dst_valid(fir_in_valid_i),
+    .overrun(cdc_fir_i_overrun)
 );
 
-cdc_adc_to_processing #(
-    .WIDTH(18),
-    .STAGES(3)
+cdc_adc_to_processing #(
+    .WIDTH(18),
+    .STAGES(3)
 )CDC_FIR_q(
     .src_clk(clk_400m),
     .dst_clk(clk_100m),
     .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
-    .src_data(cic_q_out),
-    .src_valid(cic_valid_q),
-    .dst_data(fir_d_in_q),
-    .dst_valid(fir_in_valid_q)
-);
-
+    .dst_reset_n(reset_n),
+    .src_data(cic_q_out),
+    .src_valid(cic_valid_q),
+    .dst_data(fir_d_in_q),
+    .dst_valid(fir_in_valid_q),
+    .overrun(cdc_fir_q_overrun)
+);
+
+// Audit F-1.2: sticky-latch the two per-lane overrun pulses in the 400 MHz
+// domain and expose a single module-level flag. Cleared only by
+// reset_monitors (or reset_n via reset_400m), matching the other DDC
+// diagnostic latches (overflow/saturation).
+reg  cdc_cic_fir_overrun_sticky;
+always @(posedge clk_400m) begin
+    if (reset_400m || reset_monitors)                         cdc_cic_fir_overrun_sticky <= 1'b0;
+    else if (cdc_fir_i_overrun || cdc_fir_q_overrun)          cdc_cic_fir_overrun_sticky <= 1'b1;
+end
+assign cdc_cic_fir_overrun = cdc_cic_fir_overrun_sticky;
+
 // ============================================================================
 // FIR Filter Instances
 // ============================================================================
 
-// FIR I channel
-fir_lowpass_parallel_enhanced fir_i_inst (
-    .clk(clk_100m),
-    .reset_n(reset_n),
-    .data_in(fir_d_in_i),  // Use synchronized data
-    .data_valid(fir_in_valid_i),  // Use synchronized valid
-    .data_out(fir_i_out),
-    .data_out_valid(fir_valid_i),
-    .fir_ready(fir_i_ready),
-    .filter_overflow()
-);
-
-// FIR Q channel  
-fir_lowpass_parallel_enhanced fir_q_inst (
-    .clk(clk_100m),
-    .reset_n(reset_n),
-    .data_in(fir_d_in_q),  // Use synchronized data
-    .data_valid(fir_in_valid_q),  // Use synchronized valid
-    .data_out(fir_q_out),
-    .data_out_valid(fir_valid_q),
-    .fir_ready(fir_q_ready),
-    .filter_overflow()
-);
-
-assign fir_valid = fir_valid_i & fir_valid_q;
-
-// ============================================================================
-// Enhanced Output Stage
-// ============================================================================
-always @(posedge clk_100m or negedge reset_n) begin
-    if (!reset_n) begin
-        baseband_i_reg <= 0;
-        baseband_q_reg <= 0;
-        baseband_valid_reg <= 0;
-    end else if (fir_valid) begin
-        baseband_i_reg <= fir_i_out;
-        baseband_q_reg <= fir_q_out;
-        baseband_valid_reg <= 1;
-    end else begin
-        baseband_valid_reg <= 0;
-    end
-end
-
-
-// ============================================================================
-// Output Assignments
-// ============================================================================
-assign baseband_i = baseband_i_reg;
-assign baseband_q = baseband_q_reg;
+// FIR overflow flags (audit F-6.2 — previously dangling, now OR'd into
+// module-level filter_overflow so the receiver can see FIR arithmetic overflow)
+wire fir_i_overflow;
+wire fir_q_overflow;
+
+// FIR I channel
+fir_lowpass_parallel_enhanced fir_i_inst (
+    .clk(clk_100m),
+    .reset_n(reset_n),
+    .data_in(fir_d_in_i),  // Use synchronized data
+    .data_valid(fir_in_valid_i),  // Use synchronized valid
+    .data_out(fir_i_out),
+    .data_out_valid(fir_valid_i),
+    .fir_ready(fir_i_ready),
+    .filter_overflow(fir_i_overflow)
+);
+
+// FIR Q channel
+fir_lowpass_parallel_enhanced fir_q_inst (
+    .clk(clk_100m),
+    .reset_n(reset_n),
+    .data_in(fir_d_in_q),  // Use synchronized data
+    .data_valid(fir_in_valid_q),  // Use synchronized valid
+    .data_out(fir_q_out),
+    .data_out_valid(fir_valid_q),
+    .fir_ready(fir_q_ready),
+    .filter_overflow(fir_q_overflow)
+);
+
+assign fir_valid = fir_valid_i & fir_valid_q;
+assign filter_overflow = fir_i_overflow | fir_q_overflow;
+
+// ============================================================================
+// Enhanced Output Stage
+// ============================================================================
+always @(posedge clk_100m or negedge reset_n) begin
+    if (!reset_n) begin
+        baseband_i_reg <= 0;
+        baseband_q_reg <= 0;
+        baseband_valid_reg <= 0;
+    end else if (fir_valid) begin
+        baseband_i_reg <= fir_i_out;
+        baseband_q_reg <= fir_q_out;
+        baseband_valid_reg <= 1;
+    end else begin
+        baseband_valid_reg <= 0;
+    end
+end
+
+
+// ============================================================================
+// Output Assignments
+// ============================================================================
+assign baseband_i = baseband_i_reg;
+assign baseband_q = baseband_q_reg;
 assign baseband_valid_i = baseband_valid_reg;
-assign baseband_valid_q = baseband_valid_reg;
-assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
-assign mixer_saturation = overflow_detected;
-assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
-
-// ============================================================================
-// Enhanced Debug and Monitoring
-// ============================================================================
+assign baseband_valid_q = baseband_valid_reg;
+assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
+assign mixer_saturation = overflow_detected;
+assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
+
+// ============================================================================
+// Enhanced Debug and Monitoring
+// ============================================================================
 reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
 
 `ifdef SIMULATION
@@ -699,10 +731,10 @@ always @(posedge clk_100m) begin
                  baseband_i, baseband_q, debug_bb_count);
     end
 end
-`endif
-
-// In ddc_400m.v, add these debug signals:
-
+`endif
+
+// In ddc_400m.v, add these debug signals:
+
 // Debug monitoring (simulation only)
 `ifdef SIMULATION
 reg [31:0] debug_adc_count = 0;
@@ -723,58 +755,67 @@ always @(posedge clk_100m) begin
                  baseband_i, baseband_q, debug_baseband_count, $time);
     end
 end
-`endif
-
-
-endmodule
-
-// ============================================================================
-// Enhanced Phase Dithering Module
-// ============================================================================
-`timescale 1ns / 1ps
-
-module lfsr_dither_enhanced #(
-    parameter DITHER_WIDTH = 8  // Increased for better dithering
-)(
-    input wire clk,
-    input wire reset_n,
-    input wire enable,
-    output wire [DITHER_WIDTH-1:0] dither_out
-);
-
-reg [DITHER_WIDTH-1:0] lfsr_reg;
-reg [15:0] cycle_counter;
-reg lock_detected;
-
-// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
-wire feedback;
-
-generate
-    if (DITHER_WIDTH == 4) begin
-        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
-    end else if (DITHER_WIDTH == 8) begin
-        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
-    end else begin
-        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
-    end
-endgenerate
-
-always @(posedge clk or negedge reset_n) begin
-    if (!reset_n) begin
-        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
-        cycle_counter <= 0;
-        lock_detected <= 0;
-    end else if (enable) begin
-        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
-        cycle_counter <= cycle_counter + 1;
-        
-        // Detect LFSR lock after sufficient cycles
-        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
-            lock_detected <= 1'b1;
-        end
-    end
-end
-
-assign dither_out = lfsr_reg;
-
-endmodule
+`endif
+
+
+endmodule
+
+// ============================================================================
+// Enhanced Phase Dithering Module
+// ============================================================================
+`timescale 1ns / 1ps
+
+module lfsr_dither_enhanced #(
+    parameter DITHER_WIDTH = 8  // Increased for better dithering
+)(
+    input wire clk,
+    input wire reset_n,
+    input wire enable,
+    output wire [DITHER_WIDTH-1:0] dither_out
+);
+
+reg [DITHER_WIDTH-1:0] lfsr_reg;
+reg [15:0] cycle_counter;
+reg lock_detected;
+
+// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
+wire feedback;
+
+generate
+    if (DITHER_WIDTH == 4) begin
+        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
+    end else if (DITHER_WIDTH == 8) begin
+        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
+    end else begin
+        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
+    end
+endgenerate
+
+// ============================================================================
+// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
+// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
+// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
+// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
+// ============================================================================
+(* max_fanout = 50 *) reg reset_h = 1'b1;
+always @(posedge clk) reset_h <= ~reset_n;
+
+always @(posedge clk) begin
+    if (reset_h) begin
+        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
+        cycle_counter <= 0;
+        lock_detected <= 0;
+    end else if (enable) begin
+        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
+        cycle_counter <= cycle_counter + 1;
+        
+        // Detect LFSR lock after sufficient cycles
+        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
+            lock_detected <= 1'b1;
+        end
+    end
+end
+
+assign dither_out = lfsr_reg;
+
+endmodule

9_Firmware/9_2_FPGA/doppler_processor.v

@@ -32,13 +32,28 @@
 //     w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
 // ============================================================================
 
+`include "radar_params.vh"
+
+// ----------------------------------------------------------------------------
+// !!! 200T 20 km MODE BROKEN — FIX BEFORE 200T BRING-UP !!!
+// RANGE_BINS and the range_bin output port default to `RP_NUM_RANGE_BINS
+// (512) / `RP_RANGE_BIN_BITS (9). In 20 km mode the upstream pipeline
+// emits `RP_OUTPUT_RANGE_BINS_20KM = 4096 bins/chirp, which the internal
+// range-bin BRAMs and address counters here cannot represent — bins
+// 512..4095 alias onto bins 0..511 and the Doppler FFT collects a
+// scrambled slow-time vector per aliased range cell.
+// Latent on XC7A50T (SUPPORT_LONG_RANGE undefined → 3 km only); will
+// corrupt all 20 km output on XC7A200T. Before 200T bring-up: scale
+// RANGE_BINS with `RP_MAX_OUTPUT_BINS, widen range_bin, and resize the
+// per-range chirp buffers, or route 20 km mode around this block.
+// ----------------------------------------------------------------------------
 module doppler_processor_optimized #(
-    parameter DOPPLER_FFT_SIZE   = 16,     // FFT size per sub-frame (was 32)
-    parameter RANGE_BINS         = 64,
-    parameter CHIRPS_PER_FRAME   = 32,     // Total chirps in frame (16+16)
-    parameter CHIRPS_PER_SUBFRAME = 16,    // Chirps per sub-frame
+    parameter DOPPLER_FFT_SIZE   = `RP_DOPPLER_FFT_SIZE,    // 16
+    parameter RANGE_BINS         = `RP_NUM_RANGE_BINS,      // 512
+    parameter CHIRPS_PER_FRAME   = `RP_CHIRPS_PER_FRAME,    // 32
+    parameter CHIRPS_PER_SUBFRAME = `RP_CHIRPS_PER_SUBFRAME, // 16
     parameter WINDOW_TYPE        = 0,      // 0=Hamming, 1=Rectangular
-    parameter DATA_WIDTH         = 16
+    parameter DATA_WIDTH         = `RP_DATA_WIDTH           // 16
 )(
     input wire clk,
     input wire reset_n,
@@ -48,7 +63,7 @@ module doppler_processor_optimized #(
     output reg [31:0] doppler_output,
     output reg doppler_valid,
     output reg [4:0] doppler_bin,      // {sub_frame, bin[3:0]}
-    output reg [5:0] range_bin,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
     output reg sub_frame,              // 0=long PRI, 1=short PRI
     output wire processing_active,
     output wire frame_complete,
@@ -57,16 +72,16 @@ module doppler_processor_optimized #(
 `ifdef FORMAL
     ,
     output wire [2:0]  fv_state,
-    output wire [10:0] fv_mem_write_addr,
-    output wire [10:0] fv_mem_read_addr,
-    output wire [5:0]  fv_write_range_bin,
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_write_addr,
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_read_addr,
+    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_write_range_bin,
     output wire [4:0]  fv_write_chirp_index,
-    output wire [5:0]  fv_read_range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_read_range_bin,
     output wire [4:0]  fv_read_doppler_index,
     output wire [9:0]  fv_processing_timeout,
     output wire        fv_frame_buffer_full,
     output wire        fv_mem_we,
-    output wire [10:0] fv_mem_waddr_r
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_waddr_r
 `endif
 );
 
@@ -115,9 +130,9 @@ localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
 // ==============================================
 // Control Registers
 // ==============================================
-reg [5:0] write_range_bin;
+reg [`RP_RANGE_BIN_BITS-1:0] write_range_bin;
 reg [4:0] write_chirp_index;
-reg [5:0] read_range_bin;
+reg [`RP_RANGE_BIN_BITS-1:0] read_range_bin;
 reg [4:0] read_doppler_index;
 reg frame_buffer_full;
 reg [9:0] chirps_received;
@@ -147,8 +162,8 @@ wire fft_output_last;
 // ==============================================
 // Addressing
 // ==============================================
-wire [10:0] mem_write_addr;
-wire [10:0] mem_read_addr;
+wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_write_addr;
+wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_read_addr;
 
 assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
 assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
@@ -180,7 +195,7 @@ reg [9:0] processing_timeout;
 
 // Memory write enable and data signals
 reg mem_we;
-reg [10:0] mem_waddr_r;
+reg [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_waddr_r;
 reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
 
 // Memory read data
@@ -531,6 +546,11 @@ xfft_16 fft_inst (
 // Status Outputs
 // ==============================================
 assign processing_active = (state != S_IDLE);
+// NOTE: frame_complete is a LEVEL, not a pulse. It is high whenever the
+// doppler processor is idle with no buffered frame. radar_receiver_final.v
+// converts this to a single-cycle rising-edge pulse before routing to
+// downstream consumers (USB FT2232H, AGC, CFAR). Do NOT connect this
+// level output directly to modules that expect a pulse.
 assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
 
 endmodule

9_Firmware/9_2_FPGA/fft_engine.v

@@ -28,13 +28,16 @@
  * Clock domain: single clock (clk), active-low async reset (reset_n).
  */
 
+// Include single source of truth for default parameters
+`include "radar_params.vh"
+
 module fft_engine #(
-    parameter N            = 1024,
-    parameter LOG2N        = 10,
+    parameter N            = `RP_FFT_SIZE,       // 2048
+    parameter LOG2N        = `RP_LOG2_FFT_SIZE,  // 11
     parameter DATA_W       = 16,
     parameter INTERNAL_W   = 32,
     parameter TWIDDLE_W    = 16,
-    parameter TWIDDLE_FILE = "fft_twiddle_1024.mem"
+    parameter TWIDDLE_FILE = "fft_twiddle_2048.mem"
 )(
     input wire clk,
     input wire reset_n,

9_Firmware/9_2_FPGA/fft_twiddle_2048.mem

@@ -0,0 +1,515 @@
+// Quarter-wave cosine ROM for 2048-point FFT
+// 512 entries, 16-bit signed Q15 ($readmemh format)
+// cos(2*pi*k/2048) for k = 0..511
+7FFF
+7FFF
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9_Firmware/9_2_FPGA/matched_filter_multi_segment.v

@@ -1,5 +1,8 @@
 `timescale 1ns / 1ps
 // matched_filter_multi_segment.v
+
+`include "radar_params.vh"
+
 module matched_filter_multi_segment (
     input wire clk,           // 100MHz
     input wire reset_n,
@@ -18,14 +21,13 @@ module matched_filter_multi_segment (
     input wire mc_new_elevation,    // Toggle for new elevation (32)
     input wire mc_new_azimuth,      // Toggle for new azimuth (50)
     
-    input wire [15:0] long_chirp_real,
-    input wire [15:0] long_chirp_imag,
-    input wire [15:0] short_chirp_real,
-    input wire [15:0] short_chirp_imag,
+    // Reference chirp (upstream memory loader selects long/short via use_long_chirp)
+    input wire [15:0] ref_chirp_real,
+    input wire [15:0] ref_chirp_imag,
     
     // Memory system interface
     output reg [1:0] segment_request,
-    output wire [9:0] sample_addr_out,  // Tell memory which sample we need
+    output wire [10:0] sample_addr_out,  // Tell memory which sample we need (11-bit for 2048)
     output reg mem_request,
     input wire mem_ready,
     
@@ -39,18 +41,18 @@ module matched_filter_multi_segment (
 );
 
 // ========== FIXED PARAMETERS ==========
-parameter BUFFER_SIZE = 1024;
-parameter LONG_CHIRP_SAMPLES = 3000;  // Still 3000 samples total
-parameter SHORT_CHIRP_SAMPLES = 50;   // 0.5<EFBFBD>s @ 100MHz
-parameter OVERLAP_SAMPLES = 128;      // Standard for 1024-pt FFT
-parameter SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES;  // 896 samples
-parameter DEBUG = 1;                  // Debug output control
+parameter BUFFER_SIZE = `RP_FFT_SIZE;              // 2048
+parameter LONG_CHIRP_SAMPLES = 3000;               // Still 3000 samples total
+parameter SHORT_CHIRP_SAMPLES = 50;                // 0.5 us @ 100MHz
+parameter OVERLAP_SAMPLES = `RP_OVERLAP_SAMPLES;   // 128
+parameter SEGMENT_ADVANCE = `RP_SEGMENT_ADVANCE;   // 2048 - 128 = 1920 samples
+parameter DEBUG = 1;                               // Debug output control
 
 // Calculate segments needed with overlap
-// For 3072 samples with 128 overlap: 
-// Segments = ceil((3072 - 128) / 896) = ceil(2944/896) = 4
-parameter LONG_SEGMENTS = 4;          // Now exactly 4 segments!
-parameter SHORT_SEGMENTS = 1;         // 50 samples padded to 1024
+// For 3000 samples with 128 overlap:
+// Segments = ceil((3000 - 2048) / 1920) + 1 = ceil(952/1920) + 1 = 2
+parameter LONG_SEGMENTS = `RP_LONG_SEGMENTS_3KM;   // 2 segments
+parameter SHORT_SEGMENTS = 1;                      // 50 samples padded to 2048
 
 // ========== FIXED INTERNAL SIGNALS ==========
 reg signed [31:0] pc_i, pc_q;
@@ -59,19 +61,19 @@ reg pc_valid;
 // Dual buffer for overlap-save — BRAM inferred for synthesis
 (* ram_style = "block" *) reg signed [15:0] input_buffer_i [0:BUFFER_SIZE-1];
 (* ram_style = "block" *) reg signed [15:0] input_buffer_q [0:BUFFER_SIZE-1];
-reg [10:0] buffer_write_ptr;
-reg [10:0] buffer_read_ptr;
+reg [11:0] buffer_write_ptr;    // 12-bit for 0..2048
+reg [11:0] buffer_read_ptr;     // 12-bit for 0..2048
 reg buffer_has_data;
 reg buffer_processing;
 reg [15:0] chirp_samples_collected;
 
 // BRAM write port signals
 reg        buf_we;
-reg [9:0]  buf_waddr;
+reg [10:0] buf_waddr;           // 11-bit for 0..2047
 reg signed [15:0] buf_wdata_i, buf_wdata_q;
 
 // BRAM read port signals
-reg [9:0]  buf_raddr;
+reg [10:0] buf_raddr;           // 11-bit for 0..2047
 reg signed [15:0] buf_rdata_i, buf_rdata_q;
 
 // State machine
@@ -94,15 +96,22 @@ reg chirp_complete;
 reg saw_chain_output;             // Flag: chain started producing output
 
 // Overlap cache — captured during ST_PROCESSING, written back in ST_OVERLAP_COPY
+// Uses sync-only write block to allow distributed RAM inference (not FFs).
+// 128 entries = distributed RAM (LUTRAM), NOT BRAM (too shallow).
 reg signed [15:0] overlap_cache_i [0:OVERLAP_SAMPLES-1];
 reg signed [15:0] overlap_cache_q [0:OVERLAP_SAMPLES-1];
 reg [7:0] overlap_copy_count;
 
+// Overlap cache write port signals (driven from FSM, used in sync-only block)
+reg        ov_we;
+reg [6:0]  ov_waddr;
+reg signed [15:0] ov_wdata_i, ov_wdata_q;
+
 // Microcontroller sync detection
 reg mc_new_chirp_prev, mc_new_elevation_prev, mc_new_azimuth_prev;
-wire chirp_start_pulse = mc_new_chirp && !mc_new_chirp_prev;
-wire elevation_change_pulse = mc_new_elevation && !mc_new_elevation_prev;
-wire azimuth_change_pulse = mc_new_azimuth && !mc_new_azimuth_prev;
+wire chirp_start_pulse = mc_new_chirp ^ mc_new_chirp_prev;           // Toggle-to-pulse (any edge)
+wire elevation_change_pulse = mc_new_elevation ^ mc_new_elevation_prev; // Toggle-to-pulse
+wire azimuth_change_pulse = mc_new_azimuth ^ mc_new_azimuth_prev;     // Toggle-to-pulse
 
 // Processing chain signals
 wire [15:0] fft_pc_i, fft_pc_q;
@@ -115,7 +124,7 @@ reg fft_input_valid;
 reg fft_start;
 
 // ========== SAMPLE ADDRESS OUTPUT ==========
-assign sample_addr_out = buffer_read_ptr;
+assign sample_addr_out = buffer_read_ptr[10:0];
 
 // ========== MICROCONTROLLER SYNC ==========
 always @(posedge clk or negedge reset_n) begin
@@ -152,6 +161,16 @@ always @(posedge clk) begin
     end
 end
 
+// ========== OVERLAP CACHE WRITE PORT (sync only — distributed RAM inference) ==========
+// Removing async reset from memory write path prevents Vivado from
+// synthesizing the 128x16 arrays as FFs + mux trees.
+always @(posedge clk) begin
+    if (ov_we) begin
+        overlap_cache_i[ov_waddr] <= ov_wdata_i;
+        overlap_cache_q[ov_waddr] <= ov_wdata_q;
+    end
+end
+
 // ========== BRAM READ PORT (synchronous, no async reset) ==========
 always @(posedge clk) begin
     buf_rdata_i <= input_buffer_i[buf_raddr];
@@ -183,12 +202,17 @@ always @(posedge clk or negedge reset_n) begin
         buf_wdata_i <= 0;
         buf_wdata_q <= 0;
         buf_raddr <= 0;
+        ov_we <= 0;
+        ov_waddr <= 0;
+        ov_wdata_i <= 0;
+        ov_wdata_q <= 0;
         overlap_copy_count <= 0;
     end else begin
         pc_valid <= 0;
         mem_request <= 0;
         fft_input_valid <= 0;
         buf_we <= 0;  // Default: no write
+        ov_we <= 0;   // Default: no overlap write
         
         case (state)
             ST_IDLE: begin
@@ -223,7 +247,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (ddc_valid && buffer_write_ptr < BUFFER_SIZE) begin
                     // Store in buffer via BRAM write port
                     buf_we <= 1;
-                    buf_waddr <= buffer_write_ptr[9:0];
+                    buf_waddr <= buffer_write_ptr[10:0];
                     buf_wdata_i <= ddc_i[17:2] + ddc_i[1];
                     buf_wdata_q <= ddc_q[17:2] + ddc_q[1];
                     
@@ -244,6 +268,7 @@ always @(posedge clk or negedge reset_n) begin
                     if (!use_long_chirp) begin
                         if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
                             state <= ST_ZERO_PAD;
+                            chirp_complete <= 1;  // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
                             `ifdef SIMULATION
                             $display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
                                      chirp_samples_collected + 1);
@@ -257,8 +282,8 @@ always @(posedge clk or negedge reset_n) begin
                 // missing the transition when buffer_write_ptr updates via
                 // non-blocking assignment one cycle after the last write.
                 //
-                // Overlap-save fix: fill the FULL 1024-sample buffer before
-                // processing.  For segment 0 this means 1024 fresh samples.
+                // Overlap-save fix: fill the FULL FFT_SIZE-sample buffer before
+                // processing.  For segment 0 this means FFT_SIZE fresh samples.
                 // For segments 1+, write_ptr starts at OVERLAP_SAMPLES (128)
                 // so we collect 896 new samples to fill the buffer.
                 if (use_long_chirp) begin
@@ -295,7 +320,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_ZERO_PAD: begin
                 // Zero-pad remaining buffer via BRAM write port
                 buf_we <= 1;
-                buf_waddr <= buffer_write_ptr[9:0];
+                buf_waddr <= buffer_write_ptr[10:0];
                 buf_wdata_i <= 16'd0;
                 buf_wdata_q <= 16'd0;
                 buffer_write_ptr <= buffer_write_ptr + 1;
@@ -315,7 +340,7 @@ always @(posedge clk or negedge reset_n) begin
             
             ST_WAIT_REF: begin
                 // Wait for memory to provide reference coefficients
-                buf_raddr <= 10'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
+                buf_raddr <= 11'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
                 if (mem_ready) begin
                     // Start processing — buf_rdata[0] will be valid on FIRST clock of ST_PROCESSING
                     buffer_processing <= 1;
@@ -344,10 +369,12 @@ always @(posedge clk or negedge reset_n) begin
                     // 2. Request corresponding reference sample
                     mem_request <= 1'b1;
                     
-                    // 3. Cache tail samples for overlap-save
+                    // 3. Cache tail samples for overlap-save (via sync-only write port)
                     if (buffer_read_ptr >= SEGMENT_ADVANCE) begin
-                        overlap_cache_i[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_i;
-                        overlap_cache_q[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_q;
+                        ov_we <= 1;
+                        ov_waddr <= buffer_read_ptr - SEGMENT_ADVANCE;  // 0..OVERLAP-1
+                        ov_wdata_i <= buf_rdata_i;
+                        ov_wdata_q <= buf_rdata_q;
                     end
                     
                     // Debug every 100 samples
@@ -361,7 +388,7 @@ always @(posedge clk or negedge reset_n) begin
                     end
                     
                     // Present NEXT read address (for next cycle)
-                    buf_raddr <= buffer_read_ptr[9:0] + 10'd1;
+                    buf_raddr <= buffer_read_ptr[10:0] + 11'd1;
                     buffer_read_ptr <= buffer_read_ptr + 1;
                     
                 end else if (buffer_read_ptr >= BUFFER_SIZE) begin
@@ -382,7 +409,7 @@ always @(posedge clk or negedge reset_n) begin
             
             ST_WAIT_FFT: begin
                 // Wait for the processing chain to complete ALL outputs.
-                // The chain streams 1024 samples (fft_pc_valid=1 for 1024 clocks),
+                // The chain streams FFT_SIZE samples (fft_pc_valid=1 for FFT_SIZE clocks),
                 // then transitions to ST_DONE (9) -> ST_IDLE (0).
                 // We track when output starts (saw_chain_output) and only
                 // proceed once the chain returns to idle after outputting.
@@ -454,7 +481,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_OVERLAP_COPY: begin
                 // Write one cached overlap sample per cycle to BRAM
                 buf_we <= 1;
-                buf_waddr <= {{2{1'b0}}, overlap_copy_count};
+                buf_waddr <= {{3{1'b0}}, overlap_copy_count};
                 buf_wdata_i <= overlap_cache_i[overlap_copy_count];
                 buf_wdata_q <= overlap_cache_q[overlap_copy_count];
                 
@@ -500,11 +527,9 @@ matched_filter_processing_chain m_f_p_c(
     // Chirp Selection
     .chirp_counter(chirp_counter),
     
-    // Reference Chirp Memory Interfaces
-    .long_chirp_real(long_chirp_real),
-    .long_chirp_imag(long_chirp_imag),
-    .short_chirp_real(short_chirp_real),
-    .short_chirp_imag(short_chirp_imag),
+    // Reference Chirp Memory Interface (single pair — upstream selects long/short)
+    .ref_chirp_real(ref_chirp_real),
+    .ref_chirp_imag(ref_chirp_imag),
     
     // Output
     .range_profile_i(fft_pc_i),

9_Firmware/9_2_FPGA/matched_filter_processing_chain.v

@@ -15,26 +15,28 @@
  *   .clk, .reset_n
  *   .adc_data_i, .adc_data_q, .adc_valid      <- from input buffer
  *   .chirp_counter                              <- 6-bit frame counter
- *   .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
+ *   .ref_chirp_real/imag                     <- reference (time-domain)
  *   .range_profile_i, .range_profile_q, .range_profile_valid -> output
  *   .chain_state                                -> 4-bit status
  *
  * Clock domain: clk (100 MHz system clock)
  * Data format:  16-bit signed (Q15 fixed-point)
- * FFT size:     1024 points
+ * FFT size:     2048 points (parameterized via radar_params.vh)
  *
  * Pipeline states:
- *   IDLE -> FWD_FFT (collect 1024 samples + bit-reverse copy)
+ *   IDLE -> FWD_FFT (collect 2048 samples + bit-reverse copy)
  *        -> FWD_BUTTERFLY (forward FFT of signal)
  *        -> REF_BITREV (bit-reverse copy reference into work arrays)
  *        -> REF_BUTTERFLY (forward FFT of reference)
  *        -> MULTIPLY (conjugate multiply in freq domain)
  *        -> INV_BITREV (bit-reverse copy product)
  *        -> INV_BUTTERFLY (inverse FFT + 1/N scaling)
- *        -> OUTPUT (stream 1024 samples)
+ *        -> OUTPUT (stream 2048 samples)
  *        -> DONE -> IDLE
  */
 
+`include "radar_params.vh"
+
 module matched_filter_processing_chain (
     input wire clk,
     input wire reset_n,
@@ -48,10 +50,10 @@ module matched_filter_processing_chain (
     input wire [5:0] chirp_counter,
 
     // Reference chirp (time-domain, latency-aligned by upstream buffer)
-    input wire [15:0] long_chirp_real,
-    input wire [15:0] long_chirp_imag,
-    input wire [15:0] short_chirp_real,
-    input wire [15:0] short_chirp_imag,
+    // Upstream chirp_memory_loader_param selects long/short reference
+    // via use_long_chirp — this single pair carries whichever is active.
+    input wire [15:0] ref_chirp_real,
+    input wire [15:0] ref_chirp_imag,
 
     // Output: range profile (pulse-compressed)
     output wire signed [15:0] range_profile_i,
@@ -66,8 +68,8 @@ module matched_filter_processing_chain (
 // ============================================================================
 // PARAMETERS
 // ============================================================================
-localparam FFT_SIZE   = 1024;
-localparam ADDR_BITS  = 10;    // log2(1024)
+localparam FFT_SIZE   = `RP_FFT_SIZE;    // 2048
+localparam ADDR_BITS  = `RP_LOG2_FFT_SIZE; // log2(2048) = 11
 
 // State encoding (4-bit, up to 16 states)
 localparam [3:0] ST_IDLE           = 4'd0;
@@ -87,8 +89,8 @@ reg [3:0] state;
 // SIGNAL BUFFERS
 // ============================================================================
 // Input sample counter
-reg [ADDR_BITS:0] fwd_in_count;     // 0..1024
-reg fwd_frame_done;                  // All 1024 samples received
+reg [ADDR_BITS:0] fwd_in_count;     // 0..FFT_SIZE
+reg fwd_frame_done;                  // All FFT_SIZE samples received
 
 // Signal time-domain buffer
 reg signed [15:0] fwd_buf_i [0:FFT_SIZE-1];
@@ -175,7 +177,7 @@ always @(posedge clk or negedge reset_n) begin
 
         case (state)
         // ================================================================
-        // IDLE: Wait for valid ADC data, start collecting 1024 samples
+        // IDLE: Wait for valid ADC data, start collecting 2048 samples
         // ================================================================
         ST_IDLE: begin
             fwd_in_count   <= 0;
@@ -189,8 +191,8 @@ always @(posedge clk or negedge reset_n) begin
                 // Store first sample (signal + reference)
                 fwd_buf_i[0] <= $signed(adc_data_i);
                 fwd_buf_q[0] <= $signed(adc_data_q);
-                ref_buf_i[0] <= $signed(long_chirp_real);
-                ref_buf_q[0] <= $signed(long_chirp_imag);
+                ref_buf_i[0] <= $signed(ref_chirp_real);
+                ref_buf_q[0] <= $signed(ref_chirp_imag);
                 fwd_in_count <= 1;
                 state        <= ST_FWD_FFT;
             end
@@ -198,6 +200,7 @@ always @(posedge clk or negedge reset_n) begin
 
         // ================================================================
         // FWD_FFT: Collect remaining samples, then bit-reverse copy signal
+        // (2048 samples total)
         // ================================================================
         ST_FWD_FFT: begin
             if (!fwd_frame_done) begin
@@ -205,8 +208,8 @@ always @(posedge clk or negedge reset_n) begin
                 if (adc_valid && fwd_in_count < FFT_SIZE) begin
                     fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
                     fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
-                    ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
-                    ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
+                    ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
+                    ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
                     fwd_in_count <= fwd_in_count + 1;
                 end
 
@@ -437,7 +440,7 @@ always @(posedge clk or negedge reset_n) begin
                 end
             end
 
-            // Scale by 1/N (right shift by log2(1024) = 10) and store
+            // Scale by 1/N (right shift by log2(2048) = 11) and store
             for (i = 0; i < FFT_SIZE; i = i + 1) begin : ifft_scale
                 reg signed [31:0] scaled_re, scaled_im;
                 scaled_re = work_re[i] >>> ADDR_BITS;
@@ -467,7 +470,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // OUTPUT: Stream out 1024 range profile samples, one per clock
+        // OUTPUT: Stream out 2048 range profile samples, one per clock
         // ================================================================
         ST_OUTPUT: begin
             if (out_count < FFT_SIZE) begin
@@ -531,16 +534,16 @@ end
 // ============================================================================
 // SYNTHESIS IMPLEMENTATION — Radix-2 DIT FFT via fft_engine
 // ============================================================================
-// Uses a single fft_engine instance (1024-pt) reused 3 times:
+// Uses a single fft_engine instance (2048-pt) reused 3 times:
 //   1. Forward FFT of signal
 //   2. Forward FFT of reference
 //   3. Inverse FFT of conjugate product
 // Conjugate multiply done via frequency_matched_filter (4-stage pipeline).
 //
 // Buffer scheme (BRAM-inferrable):
-//   sig_buf[1024]:  ADC input -> signal FFT output
-//   ref_buf[1024]:  Reference input -> reference FFT output
-//   prod_buf[1024]: Conjugate multiply output -> IFFT output
+//   sig_buf[2048]:  ADC input -> signal FFT output
+//   ref_buf[2048]:  Reference input -> reference FFT output
+//   prod_buf[2048]: Conjugate multiply output -> IFFT output
 //
 // Memory access is INSIDE always @(posedge clk) blocks (no async reset)
 // using local blocking variables. This eliminates NBA race conditions
@@ -552,12 +555,12 @@ end
 //   out_primed   — for output streaming
 // ============================================================================
 
-localparam FFT_SIZE  = 1024;
-localparam ADDR_BITS = 10;
+localparam FFT_SIZE  = `RP_FFT_SIZE;    // 2048
+localparam ADDR_BITS = `RP_LOG2_FFT_SIZE; // 11
 
 // State encoding
 localparam [3:0] ST_IDLE     = 4'd0,
-                 ST_COLLECT  = 4'd1,   // Collect 1024 ADC + ref samples
+                 ST_COLLECT  = 4'd1,   // Collect FFT_SIZE ADC + ref samples
                  ST_SIG_FFT  = 4'd2,   // Forward FFT of signal
                  ST_SIG_CAP  = 4'd3,   // Capture signal FFT output
                  ST_REF_FFT  = 4'd4,   // Forward FFT of reference
@@ -565,7 +568,7 @@ localparam [3:0] ST_IDLE     = 4'd0,
                  ST_MULTIPLY = 4'd6,   // Conjugate multiply (pipelined)
                  ST_INV_FFT  = 4'd7,   // Inverse FFT of product
                  ST_INV_CAP  = 4'd8,   // Capture IFFT output
-                 ST_OUTPUT   = 4'd9,   // Stream 1024 results
+                 ST_OUTPUT   = 4'd9,   // Stream FFT_SIZE results
                  ST_DONE     = 4'd10;
 
 reg [3:0] state;
@@ -588,11 +591,11 @@ reg signed [15:0] prod_rdata_i, prod_rdata_q;
 // ============================================================================
 // COUNTERS
 // ============================================================================
-reg [ADDR_BITS:0] collect_count;   // 0..1024 for sample collection
-reg [ADDR_BITS:0] feed_count;      // 0..1024 for feeding FFT engine
-reg [ADDR_BITS:0] cap_count;       // 0..1024 for capturing FFT output
-reg [ADDR_BITS:0] mult_count;      // 0..1024 for multiply feeding
-reg [ADDR_BITS:0] out_count;       // 0..1024 for output streaming
+reg [ADDR_BITS:0] collect_count;   // 0..FFT_SIZE for sample collection
+reg [ADDR_BITS:0] feed_count;      // 0..FFT_SIZE for feeding FFT engine
+reg [ADDR_BITS:0] cap_count;       // 0..FFT_SIZE for capturing FFT output
+reg [ADDR_BITS:0] mult_count;      // 0..FFT_SIZE for multiply feeding
+reg [ADDR_BITS:0] out_count;       // 0..FFT_SIZE for output streaming
 
 // BRAM read latency pipeline flags
 reg feed_primed;   // 1 = BRAM rdata valid for feed operations
@@ -617,7 +620,7 @@ fft_engine #(
     .DATA_W(16),
     .INTERNAL_W(32),
     .TWIDDLE_W(16),
-    .TWIDDLE_FILE("fft_twiddle_1024.mem")
+    .TWIDDLE_FILE("fft_twiddle_2048.mem")
 ) fft_inst (
     .clk(clk),
     .reset_n(reset_n),
@@ -775,16 +778,16 @@ always @(posedge clk) begin : ref_bram_port
         if (adc_valid) begin
             we      = 1'b1;
             addr    = 0;
-            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(long_chirp_imag);
+            wdata_i = $signed(ref_chirp_real);
+            wdata_q = $signed(ref_chirp_imag);
         end
     end
     ST_COLLECT: begin
         if (adc_valid && collect_count < FFT_SIZE) begin
             we      = 1'b1;
             addr    = collect_count[ADDR_BITS-1:0];
-            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(long_chirp_imag);
+            wdata_i = $signed(ref_chirp_real);
+            wdata_q = $signed(ref_chirp_imag);
         end
     end
     ST_REF_FFT: begin
@@ -968,7 +971,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // COLLECT: Gather 1024 ADC + reference samples
+        // COLLECT: Gather 2048 ADC + reference samples
         // Writes happen in sig/ref BRAM ports (they see state==ST_COLLECT)
         // ================================================================
         ST_COLLECT: begin
@@ -977,7 +980,7 @@ always @(posedge clk or negedge reset_n) begin
             end
 
             if (collect_count == FFT_SIZE) begin
-                // All 1024 samples collected — start signal FFT
+                // All 2048 samples collected — start signal FFT
                 state       <= ST_SIG_FFT;
                 fft_start   <= 1'b1;
                 fft_inverse <= 1'b0;  // Forward FFT
@@ -1091,7 +1094,7 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MULTIPLY: Stream sig FFT and ref FFT through freq_matched_filter
         // Both sig_buf and ref_buf are read simultaneously (separate BRAM
-        // ports). Pipeline latency = 4 clocks. Feed 1024 pairs, then flush.
+        // ports). Pipeline latency = 4 clocks. Feed 2048 pairs, then flush.
         // ================================================================
         ST_MULTIPLY: begin
             if (mult_count < FFT_SIZE) begin
@@ -1180,7 +1183,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // OUTPUT: Stream 1024 range profile samples
+        // OUTPUT: Stream 2048 range profile samples
         // BRAM read latency: present address, data valid next cycle.
         // ================================================================
         ST_OUTPUT: begin

9_Firmware/9_2_FPGA/mti_canceller.v

@@ -19,25 +19,46 @@
  *     mti_out_i[r] = current_i[r] - previous_i[r]
  *     mti_out_q[r] = current_q[r] - previous_q[r]
  *
- * The previous chirp's 64 range bins are stored in a small BRAM.
+ * The previous chirp's 512 range bins are stored in BRAM (inferred via
+ * sync-only read/write always blocks — NO async reset on memory arrays).
  * On the very first chirp after reset (or enable), there is no previous
  * data — output is zero (muted) for that first chirp.
  *
- * When mti_enable=0, the module is a transparent pass-through with zero
- * latency penalty (data goes straight through combinationally registered).
+ * When mti_enable=0, the module is a transparent pass-through.
  *
- * Resources:
- *   - 2 BRAM18 (64 x 16-bit I + 64 x 16-bit Q) or distributed RAM
- *   - ~30 LUTs (subtract + mux)
- *   - ~40 FFs (pipeline + control)
+ * BRAM inference note:
+ *   prev_i/prev_q arrays use dedicated sync-only always blocks for read
+ *   and write. This ensures Vivado infers BRAM (RAMB18) instead of fabric
+ *   FFs + mux trees. The registered read adds 1 cycle of latency, which
+ *   is compensated by a pipeline stage on the input data path.
+ *
+ * Resources (target):
+ *   - 2 BRAM18 (512 x 16-bit I + 512 x 16-bit Q)
+ *   - ~30 LUTs (subtract + mux + saturation)
+ *   - ~80 FFs (pipeline + control)
  *   - 0 DSP48
  *
  * Clock domain: clk (100 MHz)
  */
 
+`include "radar_params.vh"
+
+// ----------------------------------------------------------------------------
+// !!! 200T 20 km MODE BROKEN — FIX BEFORE 200T BRING-UP !!!
+// The prev-chirp BRAM buffer is sized to NUM_RANGE_BINS (512) and the
+// range_bin_in port is 9 bits (`RP_RANGE_BIN_BITS). In 20 km mode the
+// upstream range_bin_decimator emits `RP_OUTPUT_RANGE_BINS_20KM = 4096
+// bins per chirp (8 segments × 512 decimated bins), which aliases into
+// the 9-bit address space and collapses bins 512..4095 onto bins 0..511.
+// On XC7A50T this is latent (SUPPORT_LONG_RANGE undefined → 3 km only),
+// but on XC7A200T with SUPPORT_LONG_RANGE the 20 km data path will
+// silently corrupt every range cell above 3 km.
+// Fix before 200T bring-up: scale NUM_RANGE_BINS/range_bin width with
+// `RP_MAX_OUTPUT_BINS, or gate MTI off entirely in 20 km mode.
+// ----------------------------------------------------------------------------
 module mti_canceller #(
-    parameter NUM_RANGE_BINS = 64,
-    parameter DATA_WIDTH     = 16
+    parameter NUM_RANGE_BINS = `RP_NUM_RANGE_BINS,    // 512
+    parameter DATA_WIDTH     = `RP_DATA_WIDTH         // 16
 ) (
     input wire clk,
     input wire reset_n,
@@ -46,46 +67,119 @@ module mti_canceller #(
     input wire signed [DATA_WIDTH-1:0] range_i_in,
     input wire signed [DATA_WIDTH-1:0] range_q_in,
     input wire                         range_valid_in,
-    input wire [5:0]                   range_bin_in,
+    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,   // 9-bit
 
     // ========== OUTPUT (to Doppler processor) ==========
     output reg signed [DATA_WIDTH-1:0] range_i_out,
     output reg signed [DATA_WIDTH-1:0] range_q_out,
     output reg                         range_valid_out,
-    output reg [5:0]                   range_bin_out,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_out,   // 9-bit
 
     // ========== CONFIGURATION ==========
     input wire mti_enable,   // 1=MTI active, 0=pass-through
 
+    // Current chirp's waveform selector (from radar_mode_controller). Used
+    // to mute MTI output across the long↔short chirp boundary in range
+    // mode 01 (long-range interleave) — without this, the first chirp of
+    // a new waveform subtracts the previous waveform's range profile,
+    // injecting a per-range-bin impulse into slow-time sample 0 of the
+    // new Doppler sub-frame that spreads across all Doppler bins.
+    input wire use_long_chirp,
+
     // ========== STATUS ==========
-    output reg mti_first_chirp  // 1 during first chirp (output muted)
+    output reg mti_first_chirp, // 1 during first chirp (output muted)
+
+    // Audit F-6.3: count of saturated samples since last reset. Saturation
+    // here produces spurious Doppler harmonics (phantom targets at ±fs/2)
+    // and was previously invisible to the MCU. Saturates at 0xFF.
+    output reg [7:0] mti_saturation_count
 );
 
 // ============================================================================
-// PREVIOUS CHIRP BUFFER (64 x 16-bit I, 64 x 16-bit Q)
+// PREVIOUS CHIRP BUFFER (512 x 16-bit I, 512 x 16-bit Q)
 // ============================================================================
-// Small enough for distributed RAM on XC7A200T (64 entries).
-// Using separate I/Q arrays for clean read/write.
+// BRAM-inferred on XC7A50T/200T (512 entries, sync-only read/write).
+// Using separate I/Q arrays for clean dual-port inference.
 
-reg signed [DATA_WIDTH-1:0] prev_i [0:NUM_RANGE_BINS-1];
-reg signed [DATA_WIDTH-1:0] prev_q [0:NUM_RANGE_BINS-1];
+(* ram_style = "block" *) reg signed [DATA_WIDTH-1:0] prev_i [0:NUM_RANGE_BINS-1];
+(* ram_style = "block" *) reg signed [DATA_WIDTH-1:0] prev_q [0:NUM_RANGE_BINS-1];
+
+// ============================================================================
+// INPUT PIPELINE STAGE (1 cycle delay to match BRAM read latency)
+// ============================================================================
+// Declarations must precede the BRAM write block that references them.
+
+reg signed [DATA_WIDTH-1:0] range_i_d1, range_q_d1;
+reg                         range_valid_d1;
+reg [`RP_RANGE_BIN_BITS-1:0] range_bin_d1;
+reg                         mti_enable_d1;
+reg                         use_long_chirp_d1;
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
+        range_i_d1        <= {DATA_WIDTH{1'b0}};
+        range_q_d1        <= {DATA_WIDTH{1'b0}};
+        range_valid_d1    <= 1'b0;
+        range_bin_d1      <= {`RP_RANGE_BIN_BITS{1'b0}};
+        mti_enable_d1     <= 1'b0;
+        use_long_chirp_d1 <= 1'b0;
+    end else begin
+        range_i_d1        <= range_i_in;
+        range_q_d1        <= range_q_in;
+        range_valid_d1    <= range_valid_in;
+        range_bin_d1      <= range_bin_in;
+        mti_enable_d1     <= mti_enable;
+        use_long_chirp_d1 <= use_long_chirp;
+    end
+end
+
+// ============================================================================
+// BRAM WRITE PORT (sync only — NO async reset for BRAM inference)
+// ============================================================================
+// Writes the current chirp sample into prev_i/prev_q for next chirp's
+// subtraction. Uses the delayed (d1) signals so the write happens 1 cycle
+// after the read address is presented, avoiding RAW hazards.
+
+always @(posedge clk) begin
+    if (range_valid_d1) begin
+        prev_i[range_bin_d1] <= range_i_d1;
+        prev_q[range_bin_d1] <= range_q_d1;
+    end
+end
+
+// ============================================================================
+// BRAM READ PORT (sync only — 1 cycle read latency)
+// ============================================================================
+// Address is always driven by range_bin_in (cycle 0). Read data appears
+// on prev_i_rd / prev_q_rd at cycle 1, aligned with the d1 pipeline stage.
+
+reg signed [DATA_WIDTH-1:0] prev_i_rd, prev_q_rd;
+
+always @(posedge clk) begin
+    prev_i_rd <= prev_i[range_bin_in];
+    prev_q_rd <= prev_q[range_bin_in];
+end
 
 // Track whether we have valid previous data
 reg has_previous;
 
-// ============================================================================
-// MTI PROCESSING
-// ============================================================================
+// Waveform of the chirp whose profile currently lives in prev_i/prev_q.
+// Latched at end-of-chirp when we mark has_previous=1. Compared against
+// the incoming chirp's waveform at its first bin (range_bin_d1 == 0) to
+// detect a long↔short transition and re-mute.
+reg prev_chirp_was_long;
+wire waveform_changed = has_previous
+                      && (use_long_chirp_d1 != prev_chirp_was_long);
 
-// Read previous chirp data (combinational)
-wire signed [DATA_WIDTH-1:0] prev_i_rd = prev_i[range_bin_in];
-wire signed [DATA_WIDTH-1:0] prev_q_rd = prev_q[range_bin_in];
+// ============================================================================
+// MTI PROCESSING (operates on d1 pipeline stage + BRAM read data)
+// ============================================================================
 
 // Compute difference with saturation
 // Subtraction can produce DATA_WIDTH+1 bits; saturate back to DATA_WIDTH.
-wire signed [DATA_WIDTH:0] diff_i_full = {range_i_in[DATA_WIDTH-1], range_i_in}
+wire signed [DATA_WIDTH:0] diff_i_full = {range_i_d1[DATA_WIDTH-1], range_i_d1}
                                         - {prev_i_rd[DATA_WIDTH-1], prev_i_rd};
-wire signed [DATA_WIDTH:0] diff_q_full = {range_q_in[DATA_WIDTH-1], range_q_in}
+wire signed [DATA_WIDTH:0] diff_q_full = {range_q_d1[DATA_WIDTH-1], range_q_d1}
                                         - {prev_q_rd[DATA_WIDTH-1], prev_q_rd};
 
 // Saturate to DATA_WIDTH bits
@@ -104,55 +198,80 @@ assign diff_q_sat = (diff_q_full > $signed({{2{1'b0}}, {(DATA_WIDTH-1){1'b1}}}))
                   ? $signed({1'b1, {(DATA_WIDTH-1){1'b0}}})
                   : diff_q_full[DATA_WIDTH-1:0];
 
+// Saturation detection (F-6.3): the top two bits of the DATA_WIDTH+1 signed
+// difference disagree iff the value exceeds the DATA_WIDTH signed range.
+wire diff_i_overflow = (diff_i_full[DATA_WIDTH] != diff_i_full[DATA_WIDTH-1]);
+wire diff_q_overflow = (diff_q_full[DATA_WIDTH] != diff_q_full[DATA_WIDTH-1]);
+
 // ============================================================================
-// MAIN LOGIC
+// MAIN OUTPUT LOGIC (operates on d1 pipeline stage)
 // ============================================================================
 always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
-        range_i_out     <= {DATA_WIDTH{1'b0}};
-        range_q_out     <= {DATA_WIDTH{1'b0}};
-        range_valid_out <= 1'b0;
-        range_bin_out   <= 6'd0;
-        has_previous    <= 1'b0;
-        mti_first_chirp <= 1'b1;
+        range_i_out          <= {DATA_WIDTH{1'b0}};
+        range_q_out          <= {DATA_WIDTH{1'b0}};
+        range_valid_out      <= 1'b0;
+        range_bin_out        <= {`RP_RANGE_BIN_BITS{1'b0}};
+        has_previous         <= 1'b0;
+        mti_first_chirp      <= 1'b1;
+        prev_chirp_was_long  <= 1'b0;
+        mti_saturation_count <= 8'd0;
     end else begin
+        // Count saturated MTI-active samples (F-6.3). Clamp at 0xFF.
+        // Uses d1 pipeline stage to align with diff_i_full/diff_q_full.
+        if (range_valid_d1 && mti_enable_d1 && has_previous
+            && (diff_i_overflow || diff_q_overflow)
+            && (mti_saturation_count != 8'hFF)) begin
+            mti_saturation_count <= mti_saturation_count + 8'd1;
+        end
         // Default: no valid output
         range_valid_out <= 1'b0;
 
-        if (range_valid_in) begin
-            // Always store current sample as "previous" for next chirp
-            prev_i[range_bin_in] <= range_i_in;
-            prev_q[range_bin_in] <= range_q_in;
+        if (range_valid_d1) begin
+            // Output path — range_bin is from the delayed pipeline
+            range_bin_out <= range_bin_d1;
 
-            // Output path
-            range_bin_out <= range_bin_in;
-
-            if (!mti_enable) begin
+            if (!mti_enable_d1) begin
                 // Pass-through mode: no MTI processing
-                range_i_out     <= range_i_in;
-                range_q_out     <= range_q_in;
+                range_i_out     <= range_i_d1;
+                range_q_out     <= range_q_d1;
                 range_valid_out <= 1'b1;
                 // Reset first-chirp state when MTI is disabled
                 has_previous    <= 1'b0;
                 mti_first_chirp <= 1'b1;
-            end else if (!has_previous) begin
-                // First chirp after enable: mute output (no subtraction possible).
-                // Still emit valid=1 with zero data so Doppler processor gets
-                // the expected number of samples per frame.
+            end else if (!has_previous || waveform_changed) begin
+                // No valid previous chirp to subtract from — either the very
+                // first chirp after reset/enable, or the long↔short boundary
+                // in range_mode=01 where the prev buffer holds a different
+                // waveform's profile. Mute output (emit zeros with valid=1
+                // so Doppler still sees the expected chirp count), overwrite
+                // prev_i/prev_q as this chirp streams through the write port,
+                // then re-arm at end-of-chirp with the CURRENT waveform tag.
                 range_i_out     <= {DATA_WIDTH{1'b0}};
                 range_q_out     <= {DATA_WIDTH{1'b0}};
                 range_valid_out <= 1'b1;
+                mti_first_chirp <= 1'b1;
 
-                // After last range bin of first chirp, mark previous as valid
-                if (range_bin_in == NUM_RANGE_BINS - 1) begin
-                    has_previous    <= 1'b1;
-                    mti_first_chirp <= 1'b0;
+                // After last range bin of this chirp, the prev buffer now
+                // holds a full copy of THIS chirp's profile — arm for the
+                // next chirp and remember which waveform was written.
+                if (range_bin_d1 == NUM_RANGE_BINS - 1) begin
+                    has_previous        <= 1'b1;
+                    mti_first_chirp     <= 1'b0;
+                    prev_chirp_was_long <= use_long_chirp_d1;
                 end
             end else begin
                 // Normal MTI: subtract previous from current
                 range_i_out     <= diff_i_sat;
                 range_q_out     <= diff_q_sat;
                 range_valid_out <= 1'b1;
+
+                // Refresh the waveform tag at end-of-chirp so the compare
+                // on the next chirp stays correct (same-waveform runs are
+                // the common case and the tag must track them).
+                if (range_bin_d1 == NUM_RANGE_BINS - 1) begin
+                    prev_chirp_was_long <= use_long_chirp_d1;
+                end
             end
         end
     end

9_Firmware/9_2_FPGA/nco_400m_enhanced.v

@@ -59,6 +59,25 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;
 
+// ============================================================================
+// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
+// ============================================================================
+// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
+// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
+// regionally, avoiding the single-LUT1 / 702-load net that caused timing
+// failure in Build N. It feeds:
+//   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
+//   - All pipeline-stage fabric FDREs (synchronous reset)
+// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
+//   I1 correctness:      reset_h == ~reset_n one cycle later
+//   I2 glitch-free:      registered output
+//   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
+//                        valid clock edge; reset_n is low on power-up anyway
+//   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
+// ============================================================================
+(* max_fanout = 50 *) reg reset_h = 1'b1;
+always @(posedge clk_400m) reset_h <= ~reset_n;
+
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];
 
@@ -135,8 +154,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;
 
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         phase_accumulator <= 32'h00000000;
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
@@ -190,8 +209,8 @@ DSP48E1 #(
     .RSTA(1'b0),
     .RSTB(1'b0),
     .RSTM(1'b0),
-    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
-    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
+    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
+    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
     .RSTALLCARRYIN(1'b0),
     .RSTALUMODE(1'b0),
     .RSTCTRL(1'b0),
@@ -245,8 +264,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
     end else if (phase_valid) begin
@@ -264,8 +283,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         lut_index_pipe_sin <= 6'b000000;
         lut_index_pipe_cos <= 6'b000000;
         quadrant_pipe      <= 2'b00;
@@ -281,8 +300,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         sin_abs_reg <= 16'h0000;
         cos_abs_reg <= 16'h7FFF;
         quadrant_reg <= 2'b00;
@@ -298,8 +317,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         sin_neg_reg <= 16'h0000;
         cos_neg_reg <= -16'h7FFF;
         sin_abs_reg2 <= 16'h0000;
@@ -318,8 +337,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         sin_out <= 16'h0000;
         cos_out <= 16'h7FFF;
     end else if (valid_pipe[4]) begin
@@ -347,8 +366,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
+always @(posedge clk_400m) begin
+    if (reset_h) begin
         valid_pipe <= 6'b000000;
         dds_ready <= 1'b0;
     end else begin

9_Firmware/9_2_FPGA/plfm_chirp_controller.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 module plfm_chirp_controller_enhanced (
     input wire clk_120m,
     input wire clk_100m,
@@ -8,6 +10,10 @@ module plfm_chirp_controller_enhanced (
     input wire new_elevation,
     input wire new_azimuth,
     input wire mixers_enable,
+    // Range mode (CDC-synchronized into clk_120m by the caller).
+    //   2'b00 = 3 km  — short chirps only (skip LONG_CHIRP/LONG_LISTEN)
+    //   2'b01 = long-range — dual chirp (first half long, second half short)
+    input wire [1:0] range_mode,
     output reg [7:0] chirp_data,
     output reg chirp_valid,
 	 output wire new_chirp_frame,
@@ -45,7 +51,7 @@ parameter T2_RADAR_LISTENING = 20940; //174.5us at 120MHz
 parameter GUARD_SAMPLES = 21048;    // 175.4us at 120MHz
 
 // Chirp and beam parameters
-parameter CHIRP_MAX = 32;
+parameter CHIRP_MAX = `RP_CHIRPS_PER_FRAME;
 parameter ELEVATION_MAX = 31;
 parameter AZIMUTH_MAX = 50;
 
@@ -78,7 +84,11 @@ reg [7:0] long_chirp_rd_data;
 assign chirp__toggling = new_chirp;
 assign elevation__toggling = new_elevation;
 assign azimuth__toggling = new_azimuth;
-assign new_chirp_frame = (current_state == IDLE && next_state == LONG_CHIRP);
+// new_chirp_frame fires on IDLE -> first active state (long or short
+// depending on range_mode).
+assign new_chirp_frame = (current_state == IDLE &&
+                          (next_state == LONG_CHIRP ||
+                           next_state == SHORT_CHIRP));
 
 // Mixer TX/RX sequencing — mutually exclusive based on chirp FSM state.
 // TX mixer active during chirp transmission, RX mixer during listen.
@@ -177,10 +187,20 @@ end
 always @(*) begin
     case (current_state)
         IDLE: begin
-            if (chirp__toggling && mixers_enable)
-                next_state = LONG_CHIRP;
-            else
+            // 3 km mode skips the long-chirp half entirely — LONG_CHIRP's
+            // 4500 m blind zone exceeds the 3 km max range, so long chirps
+            // would just pollute the receive window. Go straight to
+            // SHORT_CHIRP and let the SHORT_LISTEN -> DONE guard
+            // (chirp_counter == CHIRP_MAX-1) terminate after CHIRP_MAX
+            // short chirps.
+            if (chirp__toggling && mixers_enable) begin
+                if (range_mode == `RP_RANGE_MODE_3KM)
+                    next_state = SHORT_CHIRP;
+                else
+                    next_state = LONG_CHIRP;
+            end else begin
                 next_state = IDLE;
+            end
         end
         
         LONG_CHIRP: begin
@@ -320,6 +340,11 @@ always @(posedge clk_120m or negedge reset_n) begin
             end
             
             DONE: begin
+                // Reset chirp_counter so the next frame restarts at chirp 0.
+                // Without this, frame 2+ starts at chirp_counter == CHIRP_MAX
+                // and the LONG_LISTEN transition guard (== CHIRP_MAX/2-1)
+                // never matches on the correct chirp.
+                chirp_counter <= 0;
                 chirp_done <= 1'b1;
                 chirp_data <= 8'd128;
             end

9_Firmware/9_2_FPGA/radar_mode_controller.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 /**
  * radar_mode_controller.v
  *
@@ -18,12 +20,18 @@
  *   - 32 chirps per elevation
  *   - 31 elevations per azimuth
  *   - 50 azimuths per full scan
- *   - Each chirp: Long chirp → Listen → Guard → Short chirp → Listen
  *
- * Modes of operation:
+ * Chirp sequence depends on range_mode (host_range_mode, opcode 0x20):
+ *   range_mode 2'b00 (3 km):  All short chirps only. Long chirp blind zone
+ *     (4500 m) exceeds 3 km max range, so long chirps are useless.
+ *   range_mode 2'b01 (long-range): Dual chirp — Long chirp → Listen → Guard
+ *     → Short chirp → Listen. First half of chirps_per_elev are long, second
+ *     half are short (blind-zone fill).
+ *
+ * Modes of operation (host_radar_mode, opcode 0x01):
  *   mode[1:0]:
  *     2'b00 = STM32-driven (pass through stm32 toggle signals)
- *     2'b01 = Free-running auto-scan (internal timing)
+ *     2'b01 = Free-running auto-scan (internal timing, short chirps only)
  *     2'b10 = Single-chirp (fire one chirp per trigger, for debug)
  *     2'b11 = Reserved
  *
@@ -31,9 +39,9 @@
  */
 
 module radar_mode_controller #(
-    parameter CHIRPS_PER_ELEVATION = 32,
+    parameter CHIRPS_PER_ELEVATION  = `RP_DEF_CHIRPS_PER_ELEV,
     parameter ELEVATIONS_PER_AZIMUTH = 31,
-    parameter AZIMUTHS_PER_SCAN = 50,
+    parameter AZIMUTHS_PER_SCAN     = 50,
 
     // Timing in 100 MHz clock cycles
     // Long chirp: 30us = 3000 cycles at 100 MHz
@@ -41,18 +49,24 @@ module radar_mode_controller #(
     // Guard: 175.4us = 17540 cycles
     // Short chirp: 0.5us = 50 cycles
     // Short listen: 174.5us = 17450 cycles
-    parameter LONG_CHIRP_CYCLES   = 3000,
-    parameter LONG_LISTEN_CYCLES  = 13700,
-    parameter GUARD_CYCLES        = 17540,
-    parameter SHORT_CHIRP_CYCLES  = 50,
-    parameter SHORT_LISTEN_CYCLES = 17450
+    parameter LONG_CHIRP_CYCLES   = `RP_DEF_LONG_CHIRP_CYCLES,
+    parameter LONG_LISTEN_CYCLES  = `RP_DEF_LONG_LISTEN_CYCLES,
+    parameter GUARD_CYCLES        = `RP_DEF_GUARD_CYCLES,
+    parameter SHORT_CHIRP_CYCLES  = `RP_DEF_SHORT_CHIRP_CYCLES,
+    parameter SHORT_LISTEN_CYCLES = `RP_DEF_SHORT_LISTEN_CYCLES
 ) (
     input wire clk,
     input wire reset_n,
 
-    // Mode selection
+    // Mode selection (host_radar_mode, opcode 0x01)
     input wire [1:0] mode,          // 00=STM32, 01=auto, 10=single, 11=rsvd
 
+    // Range mode (host_range_mode, opcode 0x20)
+    // Determines chirp type selection in pass-through and auto-scan modes.
+    //   2'b00 = 3 km  (all short chirps — long blind zone > max range)
+    //   2'b01 = Long-range (dual chirp: first half long, second half short)
+    input wire [1:0] range_mode,
+
     // STM32 pass-through inputs (active in mode 00)
     input wire stm32_new_chirp,
     input wire stm32_new_elevation,
@@ -61,10 +75,8 @@ module radar_mode_controller #(
     // Single-chirp trigger (active in mode 10)
     input wire trigger,
 
-    // Gap 2: Runtime-configurable timing inputs from host USB commands.
+    // Runtime-configurable timing inputs from host USB commands.
     // When connected, these override the compile-time parameters.
-    // When left at default (tied to parameter values at instantiation),
-    // behavior is identical to pre-Gap-2.
     input wire [15:0] cfg_long_chirp_cycles,
     input wire [15:0] cfg_long_listen_cycles,
     input wire [15:0] cfg_guard_cycles,
@@ -85,7 +97,15 @@ module radar_mode_controller #(
 
     // Status
     output wire scanning,       // 1 = scan in progress
-    output wire scan_complete   // pulse when full scan done
+    output wire scan_complete,  // pulse when full scan done
+
+    // Timing-config commit strobe (see "Timing-Config Commit" note below).
+    // Held HIGH while scanning is idle (S_IDLE) and pulsed for 1 clock at
+    // every elevation/azimuth boundary so radar_system_top can atomically
+    // copy its USB-written pending timing regs into the live regs the FSM
+    // reads. Guarantees no torn (cfg_long_chirp, cfg_long_listen, ...)
+    // reconfiguration mid-frame.
+    output wire cfg_commit_strobe
 
 `ifdef FORMAL
     ,
@@ -116,6 +136,29 @@ assign fv_scan_state = scan_state;
 assign fv_timer      = timer;
 `endif
 
+// ============================================================================
+// Timing-Config Commit Strobe
+//
+// radar_system_top uses this to snapshot pending USB-written timing regs
+// (opcodes 0x10..0x14) into the live regs this FSM consumes. The strobe
+// is ASSERTED whenever it is safe to commit new timing:
+//   (a) FSM is in S_IDLE (no chirp underway)  -> held HIGH continuously
+//       so an opcode written before the first trigger takes effect on
+//       the first chirp.
+//   (b) FSM is in S_ADVANCE at the elevation/azimuth boundary (i.e.,
+//       chirp_count has reached the last chirp of the current elevation)
+//       -> pulsed for the single S_ADVANCE cycle. The next frame of
+//       CHIRPS_PER_ELEVATION chirps runs with the newly-committed set.
+//
+// Combinational (no added FF). scan_state and chirp_count are registers
+// in the same clock domain, so this wire is glitch-free relative to the
+// destination register's clock edge. Downstream is a synchronous-enable
+// FF in radar_system_top, which captures cleanly on the rising edge.
+// ============================================================================
+assign cfg_commit_strobe =
+       (scan_state == S_IDLE) ||
+       ((scan_state == S_ADVANCE) && (chirp_count >= cfg_chirps_per_elev - 1));
+
 // Edge detection for STM32 pass-through
 reg stm32_new_chirp_prev;
 reg stm32_new_elevation_prev;
@@ -156,7 +199,7 @@ always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         scan_state      <= S_IDLE;
         timer           <= 18'd0;
-        use_long_chirp  <= 1'b1;
+        use_long_chirp  <= 1'b0;  // Default short chirp (safe for 3 km mode)
         mc_new_chirp    <= 1'b0;
         mc_new_elevation <= 1'b0;
         mc_new_azimuth  <= 1'b0;
@@ -172,7 +215,12 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MODE 00: STM32-driven pass-through
         // The STM32 firmware controls timing; we just detect toggle edges
-        // and forward them to the receiver chain.
+        // and forward them to the receiver chain. Chirp type is determined
+        // by range_mode:
+        //   range_mode 00 (3 km):  ALL chirps are short (long blind zone
+        //     4500 m exceeds 3072 m max range, so long chirps are useless).
+        //   range_mode 01 (long-range): First half of chirps_per_elev are
+        //     long, second half are short (blind-zone fill).
         // ================================================================
         2'b00: begin
             // Reset auto-scan state
@@ -182,9 +230,29 @@ always @(posedge clk or negedge reset_n) begin
             // Pass through toggle signals
             if (stm32_chirp_toggle) begin
                 mc_new_chirp <= ~mc_new_chirp;  // Toggle output
-                use_long_chirp <= 1'b1;         // Default to long chirp
 
-                // Track chirp count (Gap 2: use runtime cfg_chirps_per_elev)
+                // Determine chirp type based on range_mode
+                case (range_mode)
+                `RP_RANGE_MODE_3KM: begin
+                    // 3 km mode: all short chirps
+                    use_long_chirp <= 1'b0;
+                end
+                `RP_RANGE_MODE_LONG: begin
+                    // Long-range: first half long, second half short.
+                    // chirps_per_elev is typically 32 (16 long + 16 short).
+                    // Use cfg_chirps_per_elev[5:1] as the halfway point.
+                    if (chirp_count < {1'b0, cfg_chirps_per_elev[5:1]})
+                        use_long_chirp <= 1'b1;
+                    else
+                        use_long_chirp <= 1'b0;
+                end
+                default: begin
+                    // Reserved modes: default to short chirp (safe)
+                    use_long_chirp <= 1'b0;
+                end
+                endcase
+
+                // Track chirp count
                 if (chirp_count < cfg_chirps_per_elev - 1)
                     chirp_count <= chirp_count + 1;
                 else
@@ -217,21 +285,33 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MODE 01: Free-running auto-scan
         // Internally generates chirp timing matching the transmitter.
+        // For 3 km mode (range_mode 00): short chirps only. The long chirp
+        // blind zone (4500 m) exceeds the 3072 m max range, making long
+        // chirps useless. State machine skips S_LONG_CHIRP/LISTEN/GUARD.
+        // For long-range mode (range_mode 01): full dual-chirp sequence.
+        // NOTE: Auto-scan is primarily for bench testing without STM32.
         // ================================================================
         2'b01: begin
             case (scan_state)
             S_IDLE: begin
                 // Start first chirp immediately
-                scan_state     <= S_LONG_CHIRP;
-                timer          <= 18'd0;
-                use_long_chirp <= 1'b1;
-                mc_new_chirp   <= ~mc_new_chirp;  // Toggle to start chirp
-                chirp_count    <= 6'd0;
+                timer           <= 18'd0;
+                chirp_count     <= 6'd0;
                 elevation_count <= 6'd0;
-                azimuth_count  <= 6'd0;
+                azimuth_count   <= 6'd0;
+                mc_new_chirp    <= ~mc_new_chirp;  // Toggle to start chirp
+
+                // For 3 km mode, skip directly to short chirp
+                if (range_mode == `RP_RANGE_MODE_3KM) begin
+                    scan_state     <= S_SHORT_CHIRP;
+                    use_long_chirp <= 1'b0;
+                end else begin
+                    scan_state     <= S_LONG_CHIRP;
+                    use_long_chirp <= 1'b1;
+                end
 
                 `ifdef SIMULATION
-                $display("[MODE_CTRL] Auto-scan starting");
+                $display("[MODE_CTRL] Auto-scan starting, range_mode=%0d", range_mode);
                 `endif
             end
 
@@ -285,13 +365,19 @@ always @(posedge clk or negedge reset_n) begin
 
             S_ADVANCE: begin
                 // Advance chirp/elevation/azimuth counters
-                // (Gap 2: use runtime cfg_chirps_per_elev)
                 if (chirp_count < cfg_chirps_per_elev - 1) begin
                     // Next chirp in current elevation
                     chirp_count  <= chirp_count + 1;
                     mc_new_chirp <= ~mc_new_chirp;
-                    scan_state   <= S_LONG_CHIRP;
-                    use_long_chirp <= 1'b1;
+
+                    // For 3 km mode: short chirps only, skip long phases
+                    if (range_mode == `RP_RANGE_MODE_3KM) begin
+                        scan_state     <= S_SHORT_CHIRP;
+                        use_long_chirp <= 1'b0;
+                    end else begin
+                        scan_state     <= S_LONG_CHIRP;
+                        use_long_chirp <= 1'b1;
+                    end
                 end else begin
                     chirp_count <= 6'd0;
 
@@ -300,8 +386,14 @@ always @(posedge clk or negedge reset_n) begin
                         elevation_count  <= elevation_count + 1;
                         mc_new_chirp     <= ~mc_new_chirp;
                         mc_new_elevation <= ~mc_new_elevation;
-                        scan_state       <= S_LONG_CHIRP;
-                        use_long_chirp   <= 1'b1;
+
+                        if (range_mode == `RP_RANGE_MODE_3KM) begin
+                            scan_state     <= S_SHORT_CHIRP;
+                            use_long_chirp <= 1'b0;
+                        end else begin
+                            scan_state     <= S_LONG_CHIRP;
+                            use_long_chirp <= 1'b1;
+                        end
                     end else begin
                         elevation_count <= 6'd0;
 
@@ -311,8 +403,14 @@ always @(posedge clk or negedge reset_n) begin
                             mc_new_chirp     <= ~mc_new_chirp;
                             mc_new_elevation <= ~mc_new_elevation;
                             mc_new_azimuth   <= ~mc_new_azimuth;
-                            scan_state       <= S_LONG_CHIRP;
-                            use_long_chirp   <= 1'b1;
+
+                            if (range_mode == `RP_RANGE_MODE_3KM) begin
+                                scan_state     <= S_SHORT_CHIRP;
+                                use_long_chirp <= 1'b0;
+                            end else begin
+                                scan_state     <= S_LONG_CHIRP;
+                                use_long_chirp <= 1'b1;
+                            end
                         end else begin
                             // Full scan complete — restart
                             azimuth_count   <= 6'd0;
@@ -320,8 +418,14 @@ always @(posedge clk or negedge reset_n) begin
                             mc_new_chirp    <= ~mc_new_chirp;
                             mc_new_elevation <= ~mc_new_elevation;
                             mc_new_azimuth  <= ~mc_new_azimuth;
-                            scan_state      <= S_LONG_CHIRP;
-                            use_long_chirp  <= 1'b1;
+
+                            if (range_mode == `RP_RANGE_MODE_3KM) begin
+                                scan_state     <= S_SHORT_CHIRP;
+                                use_long_chirp <= 1'b0;
+                            end else begin
+                                scan_state     <= S_LONG_CHIRP;
+                                use_long_chirp <= 1'b1;
+                            end
 
                             `ifdef SIMULATION
                             $display("[MODE_CTRL] Full scan complete, restarting");
@@ -337,16 +441,27 @@ always @(posedge clk or negedge reset_n) begin
 
         // ================================================================
         // MODE 10: Single-chirp (debug mode)
-        // Fire one long chirp per trigger pulse, no scanning.
+        // Fire one chirp per trigger pulse, no scanning.
+        // Chirp type depends on range_mode:
+        //   3 km:  short chirp only
+        //   Long-range: long chirp (for testing long-chirp path)
         // ================================================================
         2'b10: begin
             case (scan_state)
             S_IDLE: begin
                 if (trigger_pulse) begin
-                    scan_state     <= S_LONG_CHIRP;
-                    timer          <= 18'd0;
-                    use_long_chirp <= 1'b1;
-                    mc_new_chirp   <= ~mc_new_chirp;
+                    timer        <= 18'd0;
+                    mc_new_chirp <= ~mc_new_chirp;
+
+                    if (range_mode == `RP_RANGE_MODE_3KM) begin
+                        // 3 km: fire short chirp
+                        scan_state     <= S_SHORT_CHIRP;
+                        use_long_chirp <= 1'b0;
+                    end else begin
+                        // Long-range: fire long chirp
+                        scan_state     <= S_LONG_CHIRP;
+                        use_long_chirp <= 1'b1;
+                    end
                 end
             end
 
@@ -363,7 +478,27 @@ always @(posedge clk or negedge reset_n) begin
                 if (timer < cfg_long_listen_cycles - 1)
                     timer <= timer + 1;
                 else begin
-                    // Single chirp done, return to idle
+                    // Single long chirp done, return to idle
+                    timer      <= 18'd0;
+                    scan_state <= S_IDLE;
+                end
+            end
+
+            S_SHORT_CHIRP: begin
+                use_long_chirp <= 1'b0;
+                if (timer < cfg_short_chirp_cycles - 1)
+                    timer <= timer + 1;
+                else begin
+                    timer <= 18'd0;
+                    scan_state <= S_SHORT_LISTEN;
+                end
+            end
+
+            S_SHORT_LISTEN: begin
+                if (timer < cfg_short_listen_cycles - 1)
+                    timer <= timer + 1;
+                else begin
+                    // Single short chirp done, return to idle
                     timer      <= 18'd0;
                     scan_state <= S_IDLE;
                 end

9_Firmware/9_2_FPGA/radar_params.vh

@@ -0,0 +1,228 @@
+// ============================================================================
+// radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
+// ============================================================================
+//
+// ALL modules in the FPGA processing chain MUST `include this file instead of
+// hardcoding range bins, segment counts, chirp samples, or timing values.
+//
+// This file uses `define macros (not localparam) so it can be included at any
+// scope. Each consuming module should include this file inside its body and
+// optionally alias macros to localparams for readability.
+//
+// BOARD VARIANTS:
+//   SUPPORT_LONG_RANGE = 0  (50T, USB_MODE=1)  — 3 km mode only
+//   SUPPORT_LONG_RANGE = 1  (200T, USB_MODE=0) — 3 km + 20 km modes
+//
+// RADAR MODES (runtime, via host_radar_mode register, opcode 0x01):
+//   2'b00 = STM32 pass-through (production — STM32 controls chirp timing)
+//   2'b01 = Auto-scan 3 km     (FPGA-timed, short chirps only)
+//   2'b10 = Single-chirp debug (one long chirp per trigger)
+//   2'b11 = Reserved / idle
+//
+// RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
+//   2'b00 = 3 km   (default — pass-through treats all chirps as short)
+//   2'b01 = Long-range (pass-through: first half long, second half short)
+//   2'b10 = Reserved
+//   2'b11 = Reserved
+//
+// USAGE:
+//   `include "radar_params.vh"
+//   Then reference `RP_FFT_SIZE, `RP_NUM_RANGE_BINS, etc.
+//
+// PHYSICAL CONSTANTS (derived from hardware):
+//   ADC clock:           400 MSPS
+//   CIC decimation:      4x
+//   Processing rate:     100 MSPS (post-DDC)
+//   Range per sample:    c / (2 * 100e6) = 1.5 m
+//   FFT size:            2048
+//   Decimation factor:   4  (2048 FFT bins -> 512 output range bins)
+//   Range per dec. bin:  1.5 m * 4 = 6.0 m
+//   Max range (3 km):    512 * 6.0 = 3072 m
+//   Carrier frequency:   10.5 GHz
+//   IF frequency:        120 MHz
+//
+// CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
+//   Range resolution:    c / (2 * BW)
+//     20 MHz -> 7.5 m
+//     30 MHz -> 5.0 m
+//   NOTE: Range resolution is independent of range-per-bin. Resolution
+//   determines the minimum separation between two targets; range-per-bin
+//   determines the spatial sampling grid.
+// ============================================================================
+
+`ifndef RADAR_PARAMS_VH
+`define RADAR_PARAMS_VH
+
+// ============================================================================
+// BOARD VARIANT — set at synthesis time, NOT runtime
+// ============================================================================
+// Default to 50T (conservative). Override in top-level or synthesis script:
+//   +define+SUPPORT_LONG_RANGE
+// or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
+
+// Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
+// `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
+// `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
+
+// ============================================================================
+// FFT AND PROCESSING CONSTANTS (fixed, both modes)
+// ============================================================================
+
+`define RP_FFT_SIZE             2048    // Range FFT points per segment
+`define RP_LOG2_FFT_SIZE        11      // log2(2048)
+`define RP_OVERLAP_SAMPLES      128     // Overlap between adjacent segments
+`define RP_SEGMENT_ADVANCE      1920    // FFT_SIZE - OVERLAP = 2048 - 128
+`define RP_DECIMATION_FACTOR    4       // Range bin decimation (2048 -> 512)
+`define RP_NUM_RANGE_BINS       512     // FFT_SIZE / DECIMATION_FACTOR
+`define RP_RANGE_BIN_BITS       9       // ceil(log2(512))
+`define RP_DOPPLER_FFT_SIZE     16      // Per sub-frame Doppler FFT
+`define RP_CHIRPS_PER_FRAME     32      // Total chirps (16 long + 16 short)
+`define RP_CHIRPS_PER_SUBFRAME  16      // Chirps per Doppler sub-frame
+`define RP_NUM_DOPPLER_BINS     32      // 2 sub-frames * 16 = 32
+`define RP_DATA_WIDTH           16      // ADC/processing data width
+
+// ============================================================================
+// 3 KM MODE PARAMETERS (both 50T and 200T)
+// ============================================================================
+
+`define RP_LONG_CHIRP_SAMPLES_3KM   3000    // 30 us at 100 MSPS
+`define RP_LONG_SEGMENTS_3KM        2       // ceil((3000-2048)/1920) + 1 = 2
+`define RP_SHORT_CHIRP_SAMPLES      50      // 0.5 us at 100 MSPS (same both modes)
+`define RP_SHORT_SEGMENTS           1       // Single segment for short chirp
+
+// Derived 3 km limits
+`define RP_MAX_RANGE_3KM            3072    // 512 bins * 6 m = 3072 m
+
+// ============================================================================
+// 20 KM MODE PARAMETERS (200T only — Phase 2)
+// ============================================================================
+
+`define RP_LONG_CHIRP_SAMPLES_20KM  13700   // 137 us at 100 MSPS (= listen window)
+`define RP_LONG_SEGMENTS_20KM       8       // 1 + ceil((13700-2048)/1920) = 1 + 7 = 8
+`define RP_OUTPUT_RANGE_BINS_20KM   4096    // 8 segments * 512 dec. bins each
+
+// Derived 20 km limits
+`define RP_MAX_RANGE_20KM           24576   // 4096 bins * 6 m = 24576 m
+
+// ============================================================================
+// MAX VALUES (for sizing buffers — compile-time, based on board variant)
+// ============================================================================
+
+`ifdef SUPPORT_LONG_RANGE
+  `define RP_MAX_SEGMENTS           8
+  `define RP_MAX_OUTPUT_BINS        4096
+  `define RP_MAX_CHIRP_SAMPLES      13700
+`else
+  `define RP_MAX_SEGMENTS           2
+  `define RP_MAX_OUTPUT_BINS        512
+  `define RP_MAX_CHIRP_SAMPLES      3000
+`endif
+
+// ============================================================================
+// BIT WIDTHS (derived from MAX values)
+// ============================================================================
+
+// Segment index: ceil(log2(MAX_SEGMENTS))
+//   50T:  log2(2) = 1 bit  (use 2 for safety)
+//   200T: log2(8) = 3 bits
+`ifdef SUPPORT_LONG_RANGE
+  `define RP_SEGMENT_IDX_WIDTH      3
+  `define RP_RANGE_BIN_WIDTH_MAX    12      // ceil(log2(4096))
+  `define RP_DOPPLER_MEM_ADDR_W     17      // ceil(log2(4096*32)) = 17
+  `define RP_CFAR_MAG_ADDR_W        17      // ceil(log2(4096*32)) = 17
+`else
+  `define RP_SEGMENT_IDX_WIDTH      2
+  `define RP_RANGE_BIN_WIDTH_MAX    9       // ceil(log2(512))
+  `define RP_DOPPLER_MEM_ADDR_W     14      // ceil(log2(512*32)) = 14
+  `define RP_CFAR_MAG_ADDR_W        14      // ceil(log2(512*32)) = 14
+`endif
+
+// Derived depths (for memory declarations)
+// Usage: reg [15:0] mem [0:`RP_DOPPLER_MEM_DEPTH-1];
+`define RP_DOPPLER_MEM_DEPTH    (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
+`define RP_CFAR_MAG_DEPTH       (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
+
+// ============================================================================
+// CHIRP TIMING DEFAULTS (100 MHz clock cycles)
+// ============================================================================
+// Reset defaults for host-configurable timing registers.
+// Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
+
+`define RP_DEF_LONG_CHIRP_CYCLES    3000    // 30 us
+`define RP_DEF_LONG_LISTEN_CYCLES   13700   // 137 us
+`define RP_DEF_GUARD_CYCLES         17540   // 175.4 us
+`define RP_DEF_SHORT_CHIRP_CYCLES   50      // 0.5 us
+`define RP_DEF_SHORT_LISTEN_CYCLES  17450   // 174.5 us
+`define RP_DEF_CHIRPS_PER_ELEV      32
+
+// ============================================================================
+// BLIND ZONE CONSTANTS (informational, for comments and GUI)
+// ============================================================================
+// Long chirp blind zone:  c * 30 us / 2 = 4500 m
+// Short chirp blind zone: c * 0.5 us / 2 = 75 m
+
+`define RP_LONG_BLIND_ZONE_M        4500
+`define RP_SHORT_BLIND_ZONE_M       75
+
+// ============================================================================
+// PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
+// ============================================================================
+// Range per ADC sample:     1.5 m  (stored as 15 in units of 0.1 m)
+// Range per decimated bin:  6.0 m  (stored as 60 in units of 0.1 m)
+// Processing rate:         100 MSPS
+
+`define RP_RANGE_PER_SAMPLE_DM      15      // 1.5 m in decimeters
+`define RP_RANGE_PER_BIN_DM         60      // 6.0 m in decimeters
+`define RP_PROCESSING_RATE_MHZ      100
+
+// ============================================================================
+// AGC DEFAULTS
+// ============================================================================
+`define RP_DEF_AGC_TARGET           200
+`define RP_DEF_AGC_ATTACK           1
+`define RP_DEF_AGC_DECAY            1
+`define RP_DEF_AGC_HOLDOFF          4
+
+// ============================================================================
+// CFAR DEFAULTS
+// ============================================================================
+`define RP_DEF_CFAR_GUARD           2
+`define RP_DEF_CFAR_TRAIN           8
+`define RP_DEF_CFAR_ALPHA           8'h30   // 3.0 in Q4.4
+`define RP_DEF_CFAR_MODE            2'b00   // CA-CFAR
+
+// ============================================================================
+// DETECTION DEFAULTS
+// ============================================================================
+`define RP_DEF_DETECT_THRESHOLD     10000
+
+// ============================================================================
+// RADAR MODE ENCODING (host_radar_mode, opcode 0x01)
+// ============================================================================
+`define RP_MODE_STM32_PASSTHROUGH   2'b00
+`define RP_MODE_AUTO_3KM            2'b01
+`define RP_MODE_SINGLE_DEBUG        2'b10
+`define RP_MODE_RESERVED            2'b11
+
+// ============================================================================
+// RANGE MODE ENCODING (host_range_mode, opcode 0x20)
+// ============================================================================
+`define RP_RANGE_MODE_3KM           2'b00
+`define RP_RANGE_MODE_LONG          2'b01
+`define RP_RANGE_MODE_RSVD2         2'b10
+`define RP_RANGE_MODE_RSVD3         2'b11
+
+// ============================================================================
+// STREAM CONTROL (host_stream_control, opcode 0x04, 6-bit)
+// ============================================================================
+// Bits [2:0]: Stream enable mask
+//   Bit 0 = range profile stream
+//   Bit 1 = doppler map stream
+//   Bit 2 = cfar/detection stream
+// Bits [5:3]: Stream format control
+//   Bit 3 = mag_only    (0=I/Q pairs, 1=Manhattan magnitude only)
+//   Bit 4 = sparse_det  (0=dense detection flags, 1=sparse detection list)
+//   Bit 5 = reserved (was frame_decimate, not needed with mag-only fitting)
+`define RP_STREAM_CTRL_DEFAULT      6'b001_111  // all streams, mag-only mode
+
+`endif // RADAR_PARAMS_VH

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 module radar_receiver_final (
     input wire clk,           // 100MHz    
 	 input wire reset_n,
@@ -9,27 +11,35 @@ module radar_receiver_final (
     input wire [7:0] adc_d_n,        // ADC Data N (LVDS)
     input wire adc_dco_p,            // Data Clock Output P (400MHz LVDS)
     input wire adc_dco_n,            // Data Clock Output N (400MHz LVDS)
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
+    input wire adc_or_p,
+    input wire adc_or_n,
 	 output wire adc_pwdn,
-    
+
     // Chirp counter from transmitter (for matched filter indexing)
     input wire [5:0] chirp_counter,
     // Frame-start pulse from transmitter (CDC-synchronized, 1 clk_100m cycle)
     input wire tx_frame_start,
-    
+
     output wire [31:0] doppler_output,
     output wire doppler_valid,
     output wire [4:0] doppler_bin,
-    output wire [5:0] range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
     
-    // Matched filter range profile output (for USB)
+    // Raw matched-filter output (debug/bring-up)
     output wire signed [15:0] range_profile_i_out,
     output wire signed [15:0] range_profile_q_out,
     output wire range_profile_valid_out,
+
+    // Decimated 512-bin range profile (for USB bulk frames / downstream consumers)
+    output wire [15:0] decimated_range_mag_out,
+    output wire decimated_range_valid_out,
     
     // Host command inputs (Gap 4: USB Read Path, CDC-synchronized)
     // CDC-synchronized in radar_system_top.v before reaching here
     input wire [1:0] host_mode,      // Radar mode: 00=STM32, 01=auto-scan, 10=single-chirp
     input wire host_trigger,          // Single-chirp trigger pulse (1 clk cycle)
+    input wire [1:0] host_range_mode, // Range mode: 00=3km (short only), 01=long-range (dual chirp)
 
     // Gap 2: Host-configurable chirp timing (CDC-synchronized in radar_system_top.v)
     input wire [15:0] host_long_chirp_cycles,
@@ -74,7 +84,34 @@ module radar_receiver_final (
     // AGC status outputs (for status readback / STM32 outer loop)
     output wire [7:0]  agc_saturation_count, // Per-frame clipped sample count
     output wire [7:0]  agc_peak_magnitude,   // Per-frame peak (upper 8 bits)
-    output wire [3:0]  agc_current_gain      // Effective gain_shift encoding
+    output wire [3:0]  agc_current_gain,     // Effective gain_shift encoding
+
+    // DDC overflow diagnostics (audit F-6.1 — previously deleted at boundary).
+    // Not yet plumbed into the USB status packet (protocol contract is frozen);
+    // exposed here for gpio aggregation and ILA mark_debug visibility.
+    output wire        ddc_overflow_any,
+    output wire [2:0]  ddc_saturation_count,
+
+    // MTI 2-pulse canceller saturation count (audit F-6.3).
+    output wire [7:0]  mti_saturation_count_out,
+
+    // Range-bin decimator watchdog (audit F-6.4 — previously tied off
+    // with an ILA-only note). A high pulse here means the decimator
+    // FSM has not seen the expected number of input samples within
+    // its timeout window, i.e. the upstream FIR/CDC has stalled.
+    output wire        range_decim_watchdog,
+
+    // Audit F-1.2: sticky CIC→FIR CDC overrun flag. Asserts on the first
+    // silent sample drop between the 400 MHz CIC output and the 100 MHz
+    // FIR input; stays high until the next reset. OR'd into the GPIO
+    // diagnostic bit at the top level.
+    output wire        ddc_cic_fir_overrun,
+
+    // C-4: timing-config commit strobe from rmc. radar_system_top uses
+    // this to atomically snapshot pending USB-written timing regs
+    // (opcodes 0x10..0x14) into the live regs this RX chain consumes,
+    // eliminating the mid-frame torn-reconfig hazard.
+    output wire        cfg_commit_strobe
 );
 
 // ========== INTERNAL SIGNALS ==========
@@ -104,9 +141,9 @@ wire [7:0] gc_saturation_count;  // Diagnostic: per-frame clipped sample counter
 wire [7:0] gc_peak_magnitude;    // Diagnostic: per-frame peak magnitude
 wire [3:0] gc_current_gain;      // Diagnostic: effective gain_shift
 
-// Reference signals for the processing chain
-wire [15:0] long_chirp_real, long_chirp_imag;
-wire [15:0] short_chirp_real, short_chirp_imag;
+// Reference signal for the processing chain (carries long OR short ref
+// depending on use_long_chirp — selected by chirp_memory_loader_param)
+wire [15:0] ref_chirp_real, ref_chirp_imag;
 
 // ========== DOPPLER PROCESSING SIGNALS ==========
 wire [31:0] range_data_32bit;
@@ -118,20 +155,36 @@ wire [31:0] doppler_spectrum;
 wire doppler_spectrum_valid;
 wire [4:0] doppler_bin_out;
 wire doppler_processing;
-wire doppler_frame_done;
+
+// frame_complete from doppler_processor is a LEVEL signal (high whenever
+// state == S_IDLE && !frame_buffer_full). Downstream consumers (USB FT2232H,
+// AGC, CFAR) expect a single-cycle PULSE. Convert here at the source so all
+// consumers are safe.
+wire doppler_frame_done_level;  // raw level from doppler_processor
+reg  doppler_frame_done_prev;
+wire doppler_frame_done;        // rising-edge pulse (1 clk cycle)
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n)
+        doppler_frame_done_prev <= 1'b0;
+    else
+        doppler_frame_done_prev <= doppler_frame_done_level;
+end
+
+assign doppler_frame_done = doppler_frame_done_level & ~doppler_frame_done_prev;
 assign doppler_frame_done_out = doppler_frame_done;
 
 // ========== RANGE BIN DECIMATOR SIGNALS ==========
 wire signed [15:0] decimated_range_i;
 wire signed [15:0] decimated_range_q;
 wire decimated_range_valid;
-wire [5:0] decimated_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0] decimated_range_bin;  // 9-bit
 
 // ========== MTI CANCELLER SIGNALS ==========
 wire signed [15:0] mti_range_i;
 wire signed [15:0] mti_range_q;
 wire mti_range_valid;
-wire [5:0] mti_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0] mti_range_bin;  // 9-bit
 wire mti_first_chirp;
 
 // ========== RADAR MODE CONTROLLER SIGNALS ==========
@@ -149,6 +202,7 @@ radar_mode_controller rmc (
     .clk(clk),
     .reset_n(reset_n),
     .mode(host_mode),                     // Controlled by host via USB (default: 2'b01 auto-scan)
+    .range_mode(host_range_mode),          // Range mode: 00=3km, 01=long-range (drives chirp type)
     .stm32_new_chirp(stm32_new_chirp_rx),
     .stm32_new_elevation(stm32_new_elevation_rx),
     .stm32_new_azimuth(stm32_new_azimuth_rx),
@@ -168,7 +222,8 @@ radar_mode_controller rmc (
     .elevation_count(rmc_elevation_count),
     .azimuth_count(rmc_azimuth_count),
     .scanning(rmc_scanning),
-    .scan_complete(rmc_scan_complete)
+    .scan_complete(rmc_scan_complete),
+    .cfg_commit_strobe(cfg_commit_strobe)
 );
 wire clk_400m;
 
@@ -185,18 +240,43 @@ wire adc_valid;            // Data valid signal
 // ADC power-down control (directly tie low = ADC always on)
 assign adc_pwdn = 1'b0;
 
+wire adc_overrange_400m;
 ad9484_interface_400m adc (
 	.adc_d_p(adc_d_p),
 	.adc_d_n(adc_d_n),
 	.adc_dco_p(adc_dco_p),
 	.adc_dco_n(adc_dco_n),
+	.adc_or_p(adc_or_p),
+	.adc_or_n(adc_or_n),
 	.sys_clk(clk),
 	.reset_n(reset_n),
 	.adc_data_400m(adc_data_cmos),
 	.adc_data_valid_400m(adc_valid),
-	.adc_dco_bufg(clk_400m)
+	.adc_dco_bufg(clk_400m),
+	.adc_overrange_400m(adc_overrange_400m)
 );
 
+// Audit F-0.1: stickify the 400 MHz OR pulse, then CDC to clk_100m via 2FF.
+// Same reasoning as ddc_cic_fir_overrun: single-bit, low→high-only once
+// latched, so a 2FF sync is sufficient for a GPIO-class diagnostic. Cleared
+// only by global reset_n.
+reg adc_overrange_sticky_400m;
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n)
+        adc_overrange_sticky_400m <= 1'b0;
+    else if (adc_overrange_400m)
+        adc_overrange_sticky_400m <= 1'b1;
+end
+
+(* ASYNC_REG = "TRUE" *) reg [1:0] adc_overrange_sync_100m;
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n)
+        adc_overrange_sync_100m <= 2'b00;
+    else
+        adc_overrange_sync_100m <= {adc_overrange_sync_100m[0], adc_overrange_sticky_400m};
+end
+wire adc_overrange_100m = adc_overrange_sync_100m[1];
+
 // NOTE: The cdc_adc_to_processing instance that was here used src_clk=dst_clk=clk_400m
 // (same clock domain — no crossing). Gray-code CDC on same-clock with fast-changing
 // ADC data corrupts samples because Gray coding only guarantees safe transfer of
@@ -211,6 +291,16 @@ wire signed [17:0] ddc_out_q;
 wire ddc_valid_i;
 wire ddc_valid_q;
 
+// DDC diagnostic signals (audit F-6.1 — all outputs previously unconnected)
+wire [1:0] ddc_status_w;
+wire [7:0] ddc_diagnostics_w;
+wire       ddc_mixer_saturation;
+wire       ddc_filter_overflow;
+
+(* mark_debug = "true" *) wire ddc_mixer_saturation_dbg = ddc_mixer_saturation;
+(* mark_debug = "true" *) wire ddc_filter_overflow_dbg  = ddc_filter_overflow;
+(* mark_debug = "true" *) wire [7:0] ddc_diagnostics_dbg = ddc_diagnostics_w;
+
 ddc_400m_enhanced ddc(
     .clk_400m(clk_400m),           // 400MHz clock from ADC DCO
     .clk_100m(clk),           // 100MHz system clock //used by the 2 FIR
@@ -219,12 +309,31 @@ ddc_400m_enhanced ddc(
     .adc_data_valid_i(adc_valid),     // Valid at 400MHz
     .adc_data_valid_q(adc_valid),     // Valid at 400MHz
     .baseband_i(ddc_out_i), // I output at 100MHz
-    .baseband_q(ddc_out_q), // Q output at 100MHz  
+    .baseband_q(ddc_out_q), // Q output at 100MHz
     .baseband_valid_i(ddc_valid_i),     // Valid at 100MHz
-	 .baseband_valid_q(ddc_valid_q),
- 	 .mixers_enable(1'b1)
+    .baseband_valid_q(ddc_valid_q),
+    .mixers_enable(1'b1),
+    // Diagnostics (audit F-6.1) — previously all unconnected
+    .ddc_status(ddc_status_w),
+    .ddc_diagnostics(ddc_diagnostics_w),
+    .mixer_saturation(ddc_mixer_saturation),
+    .filter_overflow(ddc_filter_overflow),
+    // Test/debug inputs — explicit tie-low (were floating)
+    .test_mode(2'b00),
+    .test_phase_inc(16'h0000),
+    .force_saturation(1'b0),
+    .reset_monitors(1'b0),
+    .debug_sample_count(),
+    .debug_internal_i(),
+    .debug_internal_q(),
+    .cdc_cic_fir_overrun(ddc_cic_fir_overrun)
 );
 
+// Audit F-0.1: AD9484 overrange aggregated here so a single gpio_dig bit
+// covers DDC-internal saturation, FIR overflow, AND raw ADC clipping.
+assign ddc_overflow_any     = ddc_mixer_saturation | ddc_filter_overflow | adc_overrange_100m;
+assign ddc_saturation_count = ddc_diagnostics_w[7:5];
+
 ddc_input_interface ddc_if (
     .clk(clk),
     .reset_n(reset_n),
@@ -267,7 +376,7 @@ rx_gain_control gain_ctrl (
 );
 
 // 3. Dual Chirp Memory Loader
-wire [9:0] sample_addr_from_chain;
+wire [10:0] sample_addr_from_chain;
 
 chirp_memory_loader_param chirp_mem (
     .clk(clk),
@@ -281,20 +390,9 @@ chirp_memory_loader_param chirp_mem (
     .mem_ready(mem_ready)
 );
 
-// Sample address generator
-reg [9:0] sample_addr_reg;
-always @(posedge clk or negedge reset_n) begin
-    if (!reset_n) begin
-        sample_addr_reg <= 0;
-    end else if (mem_request) begin
-        sample_addr_reg <= sample_addr_reg + 1;
-        if (sample_addr_reg == 1023) sample_addr_reg <= 0;
-    end
-end
-// sample_addr_wire removed — was unused implicit wire (synthesis warning)
-
 // 4. CRITICAL: Reference Chirp Latency Buffer
-// This aligns reference data with FFT output (2159 cycle delay)
+// This aligns reference data with FFT output (3187 cycle delay)
+// TODO: verify empirically during hardware bring-up with correlation test
 wire [15:0] delayed_ref_i, delayed_ref_q;
 wire mem_ready_delayed;
 
@@ -310,11 +408,10 @@ latency_buffer #(
     .valid_out(mem_ready_delayed)
 );
 
-// Assign delayed reference signals
-assign long_chirp_real = delayed_ref_i;
-assign long_chirp_imag = delayed_ref_q;
-assign short_chirp_real = delayed_ref_i;
-assign short_chirp_imag = delayed_ref_q;
+// Assign delayed reference signals (single pair — chirp_memory_loader_param
+// selects long/short reference upstream via use_long_chirp)
+assign ref_chirp_real = delayed_ref_i;
+assign ref_chirp_imag = delayed_ref_q;
 
 // 5. Dual Chirp Matched Filter
 
@@ -326,6 +423,12 @@ wire range_valid;
 assign range_profile_i_out = range_profile_i;
 assign range_profile_q_out = range_profile_q;
 assign range_profile_valid_out = range_valid;
+// Manhattan magnitude: |I| + |Q|, saturated to 16 bits
+wire [15:0] abs_mti_i = mti_range_i[15] ? (~mti_range_i + 16'd1) : mti_range_i;
+wire [15:0] abs_mti_q = mti_range_q[15] ? (~mti_range_q + 16'd1) : mti_range_q;
+wire [16:0] manhattan_sum = {1'b0, abs_mti_i} + {1'b0, abs_mti_q};
+assign decimated_range_mag_out = manhattan_sum[16] ? 16'hFFFF : manhattan_sum[15:0];
+assign decimated_range_valid_out = mti_range_valid;
 
 matched_filter_multi_segment mf_dual (
     .clk(clk),
@@ -338,10 +441,8 @@ matched_filter_multi_segment mf_dual (
     .mc_new_chirp(mc_new_chirp),
     .mc_new_elevation(mc_new_elevation),
     .mc_new_azimuth(mc_new_azimuth),
-	 .long_chirp_real(delayed_ref_i),      // From latency buffer
-    .long_chirp_imag(delayed_ref_q),
-    .short_chirp_real(delayed_ref_i),     // Same for short chirp
-    .short_chirp_imag(delayed_ref_q),
+	 .ref_chirp_real(delayed_ref_i),       // From latency buffer (long or short ref)
+    .ref_chirp_imag(delayed_ref_q),
     .segment_request(segment_request),
     .mem_request(mem_request),
 	 .sample_addr_out(sample_addr_from_chain),
@@ -352,11 +453,11 @@ matched_filter_multi_segment mf_dual (
 );
 
 // ========== CRITICAL: RANGE BIN DECIMATOR ==========
-// Convert 1024 range bins to 64 bins for Doppler
+// Convert 2048 range bins to 512 bins for Doppler
 range_bin_decimator #(
-    .INPUT_BINS(1024),
-    .OUTPUT_BINS(64),
-    .DECIMATION_FACTOR(16)
+    .INPUT_BINS(`RP_FFT_SIZE),              // 2048
+    .OUTPUT_BINS(`RP_NUM_RANGE_BINS),       // 512
+    .DECIMATION_FACTOR(`RP_DECIMATION_FACTOR)  // 4
 ) range_decim (
     .clk(clk),
     .reset_n(reset_n),
@@ -368,8 +469,8 @@ range_bin_decimator #(
     .range_valid_out(decimated_range_valid),
     .range_bin_index(decimated_range_bin),
     .decimation_mode(2'b01),           // Peak detection mode
-    .start_bin(10'd0),
-    .watchdog_timeout()                // Diagnostic — unconnected (monitored via ILA if needed)
+    .start_bin(11'd0),
+    .watchdog_timeout(range_decim_watchdog)  // Audit F-6.4 — plumbed out
 );
 
 // ========== MTI CANCELLER (Ground Clutter Removal) ==========
@@ -377,8 +478,8 @@ range_bin_decimator #(
 // H(z) = 1 - z^{-1} → null at DC Doppler, removes stationary clutter.
 // When host_mti_enable=0: transparent pass-through.
 mti_canceller #(
-    .NUM_RANGE_BINS(64),
-    .DATA_WIDTH(16)
+    .NUM_RANGE_BINS(`RP_NUM_RANGE_BINS),    // 512
+    .DATA_WIDTH(`RP_DATA_WIDTH)             // 16
 ) mti_inst (
     .clk(clk),
     .reset_n(reset_n),
@@ -391,17 +492,19 @@ mti_canceller #(
     .range_valid_out(mti_range_valid),
     .range_bin_out(mti_range_bin),
     .mti_enable(host_mti_enable),
-    .mti_first_chirp(mti_first_chirp)
+    .use_long_chirp(use_long_chirp),
+    .mti_first_chirp(mti_first_chirp),
+    .mti_saturation_count(mti_saturation_count_out)
 );
 
 // ========== FRAME SYNC FROM TRANSMITTER ==========
 // [FPGA-001 FIXED] Use the authoritative new_chirp_frame signal from the
 // transmitter (via plfm_chirp_controller_enhanced), CDC-synchronized to
-// clk_100m in radar_system_top.  Previous code tried to derive frame
+// clk_100m in radar_system_top. Previous code tried to derive frame
 // boundaries from chirp_counter == 0, but that counter comes from the
 // transmitter path (plfm_chirp_controller_enhanced) which does NOT wrap
 // at chirps_per_elev — it overflows to N and only wraps at 6-bit rollover
-// (64).  This caused frame pulses at half the expected rate for N=32.
+// (64). This caused frame pulses at half the expected rate for N=32.
 reg tx_frame_start_prev;
 reg new_frame_pulse;
 
@@ -411,13 +514,13 @@ always @(posedge clk or negedge reset_n) begin
         new_frame_pulse <= 1'b0;
     end else begin
         new_frame_pulse <= 1'b0;
-        
+
         // Edge detect: tx_frame_start is a toggle-CDC derived pulse that
         // may be 1 clock wide.  Capture rising edge for clean 1-cycle pulse.
         if (tx_frame_start && !tx_frame_start_prev) begin
             new_frame_pulse <= 1'b1;
         end
-        
+
         tx_frame_start_prev <= tx_frame_start;
     end
 end
@@ -430,12 +533,12 @@ assign range_data_32bit = {mti_range_q, mti_range_i};
 assign range_data_valid = mti_range_valid;
 
 // ========== DOPPLER PROCESSOR ==========
-doppler_processor_optimized #(
-    .DOPPLER_FFT_SIZE(16),
-    .RANGE_BINS(64),
-    .CHIRPS_PER_FRAME(32),
-    .CHIRPS_PER_SUBFRAME(16)
-) doppler_proc (
+doppler_processor_optimized #(
+    .DOPPLER_FFT_SIZE(`RP_DOPPLER_FFT_SIZE),        // 16
+    .RANGE_BINS(`RP_NUM_RANGE_BINS),                // 512
+    .CHIRPS_PER_FRAME(`RP_CHIRPS_PER_FRAME),        // 32
+    .CHIRPS_PER_SUBFRAME(`RP_CHIRPS_PER_SUBFRAME)   // 16
+) doppler_proc (
     .clk(clk),
     .reset_n(reset_n),
     .range_data(range_data_32bit),
@@ -450,7 +553,7 @@ doppler_processor_optimized #(
     
     // Status
     .processing_active(doppler_processing),
-    .frame_complete(doppler_frame_done),
+    .frame_complete(doppler_frame_done_level),
     .status()
 );
 
@@ -498,4 +601,4 @@ assign agc_saturation_count = gc_saturation_count;
 assign agc_peak_magnitude   = gc_peak_magnitude;
 assign agc_current_gain     = gc_current_gain;
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 /**
  * radar_system_top.v
  * 
@@ -67,6 +69,9 @@ module radar_system_top (
     input wire [7:0] adc_d_n,            // ADC Data N (LVDS)
     input wire adc_dco_p,                 // Data Clock Output P (400MHz LVDS)
     input wire adc_dco_n,                 // Data Clock Output N (400MHz LVDS)
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
+    input wire adc_or_p,
+    input wire adc_or_n,
     output wire adc_pwdn,                  // ADC Power Down
     
     // ========== STM32 CONTROL INTERFACES ==========
@@ -122,7 +127,7 @@ module radar_system_top (
     output wire [31:0] dbg_doppler_data,
     output wire dbg_doppler_valid,
     output wire [4:0] dbg_doppler_bin,
-    output wire [5:0] dbg_range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0] dbg_range_bin,
     
     // System status
     output wire [3:0] system_status,
@@ -176,9 +181,11 @@ wire tx_current_chirp_sync_valid;
 wire [31:0] rx_doppler_output;
 wire rx_doppler_valid;
 wire [4:0] rx_doppler_bin;
-wire [5:0] rx_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0] rx_range_bin;
 wire [31:0] rx_range_profile;
 wire rx_range_valid;
+wire [15:0] rx_range_profile_decimated;
+wire rx_range_profile_decimated_valid;
 wire [15:0] rx_doppler_real;
 wire [15:0] rx_doppler_imag;
 wire rx_doppler_data_valid;
@@ -198,6 +205,23 @@ wire [7:0]  rx_agc_saturation_count;
 wire [7:0]  rx_agc_peak_magnitude;
 wire [3:0]  rx_agc_current_gain;
 
+// DDC overflow diagnostics (audit F-6.1) — plumbed out of receiver so the
+// DDC mixer_saturation / filter_overflow ports are no longer deleted at
+// the boundary. Aggregated into gpio_dig5 alongside AGC saturation.
+wire        rx_ddc_overflow_any;
+wire [2:0]  rx_ddc_saturation_count;
+// MTI saturation count (audit F-6.3). OR'd into gpio_dig5 for MCU visibility.
+wire [7:0]  rx_mti_saturation_count;
+// Range-bin decimator watchdog (audit F-6.4). High = decimator stalled.
+wire        rx_range_decim_watchdog;
+// CIC→FIR CDC overrun sticky (audit F-1.2). High = at least one baseband
+// sample has been silently dropped between the 400 MHz CIC and 100 MHz FIR.
+wire        rx_ddc_cic_fir_overrun;
+// C-4: timing-config commit strobe from rmc (clk_100m domain). HIGH in
+// S_IDLE and pulsed at elevation/azimuth boundaries. Used to latch the
+// pending USB-written timing regs into the live regs the RX FSM reads.
+wire        cfg_commit_strobe;
+
 // Data packing for USB
 wire [31:0] usb_range_profile;
 wire usb_range_valid;
@@ -223,7 +247,7 @@ wire [15:0] usb_cmd_value;
 reg [1:0]  host_radar_mode;
 reg        host_trigger_pulse;
 reg [15:0] host_detect_threshold;  // (was host_cfar_threshold)
-reg [2:0]  host_stream_control;
+reg [5:0]  host_stream_control;
 
 // Fix 3: Digital gain control register
 // [3]=direction: 0=amplify, 1=attenuate. [2:0]=shift amount 0..7.
@@ -234,29 +258,43 @@ reg [3:0]  host_gain_shift;
 // These override the compile-time defaults in radar_mode_controller when
 // written via USB command. Defaults match the parameter values in
 // radar_mode_controller.v so behavior is unchanged until the host writes them.
-reg [15:0] host_long_chirp_cycles;    // Opcode 0x10 (default 3000)
-reg [15:0] host_long_listen_cycles;   // Opcode 0x11 (default 13700)
-reg [15:0] host_guard_cycles;         // Opcode 0x12 (default 17540)
-reg [15:0] host_short_chirp_cycles;   // Opcode 0x13 (default 50)
-reg [15:0] host_short_listen_cycles;  // Opcode 0x14 (default 17450)
-reg [5:0]  host_chirps_per_elev;      // Opcode 0x15 (default 32)
+// C-4: Split each timing reg into pending (USB write target) and live
+// (FSM consumer). The RX radar_mode_controller pulses cfg_commit_strobe
+// at every elevation/azimuth boundary (and holds it HIGH in S_IDLE),
+// and the live regs snapshot the pending set on that strobe. This
+// guarantees that a multi-opcode GUI reconfiguration (0x10 → 0x11 →
+// 0x12, separated by USB round-trips) can never be observed
+// mid-reconfiguration by the FSM: between frames the pending set is
+// either entirely old or entirely new. Without this, a mid-chirp update
+// to cfg_long_chirp_cycles below the current timer would immediately
+// truncate the chirp and corrupt that frame's range-Doppler map.
+reg [15:0] host_long_chirp_cycles_pending;    // Opcode 0x10 (default 3000)
+reg [15:0] host_long_listen_cycles_pending;   // Opcode 0x11 (default 13700)
+reg [15:0] host_guard_cycles_pending;         // Opcode 0x12 (default 17540)
+reg [15:0] host_short_chirp_cycles_pending;   // Opcode 0x13 (default 50)
+reg [15:0] host_short_listen_cycles_pending;  // Opcode 0x14 (default 17450)
+reg [15:0] host_long_chirp_cycles;            // Live: committed at frame boundary
+reg [15:0] host_long_listen_cycles;           // Live: committed at frame boundary
+reg [15:0] host_guard_cycles;                 // Live: committed at frame boundary
+reg [15:0] host_short_chirp_cycles;           // Live: committed at frame boundary
+reg [15:0] host_short_listen_cycles;          // Live: committed at frame boundary
+reg [5:0]  host_chirps_per_elev;              // Opcode 0x15 (default 32) — has dedicated clamp logic
 reg        host_status_request;       // Opcode 0xFF (self-clearing pulse)
 
 // Fix 4: Doppler/chirps mismatch protection
-// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
-// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
-// different value, Doppler accumulation is corrupted. Clamp at command decode
-// and flag the mismatch so the host knows.
-localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
-reg        chirps_mismatch_error;     // Set if host tried to set chirps != FFT size
+// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
+// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
+// different value, Doppler accumulation is corrupted. Clamp at command decode
+// and flag the mismatch so the host knows.
+localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
+reg        chirps_mismatch_error;     // Set if host tried to set chirps != FFT size
 
-// Fix 7: Range-mode register (opcode 0x20)
-// Future-proofing for 3km/10km antenna switching.
-//   2'b00 = Auto (default — system selects based on scene)
-//   2'b01 = Short-range (3km)
-//   2'b10 = Long-range (10km)
+// Range-mode register (opcode 0x20)
+// Controls chirp type selection in the mode controller:
+//   2'b00 = 3 km mode (all short chirps — long blind zone > max range)
+//   2'b01 = Long-range (dual chirp: first half long, second half short)
+//   2'b10 = Reserved
 //   2'b11 = Reserved
-// Currently a configuration store only — antenna/timing switching TBD.
 reg [1:0]  host_range_mode;
 
 // CFAR configuration registers (host-configurable via USB)
@@ -487,7 +525,10 @@ radar_transmitter tx_inst (
     .stm32_cs_adar2_1v8(stm32_cs_adar2_1v8),
     .stm32_cs_adar3_1v8(stm32_cs_adar3_1v8),
     .stm32_cs_adar4_1v8(stm32_cs_adar4_1v8),
-    
+
+    // Host range mode (clk_100m domain; CDC'd inside radar_transmitter)
+    .host_range_mode(host_range_mode),
+
     // Beam Position Tracking
     .current_elevation(tx_current_elevation),
     .current_azimuth(tx_current_azimuth),
@@ -513,6 +554,8 @@ radar_receiver_final rx_inst (
     .adc_d_n(adc_d_n),
     .adc_dco_p(adc_dco_p),
     .adc_dco_n(adc_dco_n),
+    .adc_or_p(adc_or_p),
+    .adc_or_n(adc_or_n),
     .adc_pwdn(adc_pwdn),
     
     // Doppler Outputs
@@ -521,14 +564,16 @@ radar_receiver_final rx_inst (
     .doppler_bin(rx_doppler_bin),
     .range_bin(rx_range_bin),
     
-    // Matched filter range profile (for USB)
+    // Range-profile outputs
     .range_profile_i_out(rx_range_profile[15:0]),
     .range_profile_q_out(rx_range_profile[31:16]),
     .range_profile_valid_out(rx_range_valid),
+    .decimated_range_mag_out(rx_range_profile_decimated),
+    .decimated_range_valid_out(rx_range_profile_decimated_valid),
     
-    // Host command inputs (Gap 4: USB Read Path)
     .host_mode(host_radar_mode),
     .host_trigger(host_trigger_pulse),
+    .host_range_mode(host_range_mode),
     // Gap 2: Host-configurable chirp timing
     .host_long_chirp_cycles(host_long_chirp_cycles),
     .host_long_listen_cycles(host_long_listen_cycles),
@@ -562,7 +607,17 @@ radar_receiver_final rx_inst (
     // AGC status outputs
     .agc_saturation_count(rx_agc_saturation_count),
     .agc_peak_magnitude(rx_agc_peak_magnitude),
-    .agc_current_gain(rx_agc_current_gain)
+    .agc_current_gain(rx_agc_current_gain),
+    // DDC overflow diagnostics (audit F-6.1)
+    .ddc_overflow_any(rx_ddc_overflow_any),
+    .ddc_saturation_count(rx_ddc_saturation_count),
+    // MTI saturation count (audit F-6.3)
+    .mti_saturation_count_out(rx_mti_saturation_count),
+    // Range-bin decimator watchdog (audit F-6.4)
+    .range_decim_watchdog(rx_range_decim_watchdog),
+    .ddc_cic_fir_overrun(rx_ddc_cic_fir_overrun),
+    // C-4: timing-reg commit strobe from rmc (live regs update only when high)
+    .cfg_commit_strobe(cfg_commit_strobe)
 );
 
 // ============================================================================
@@ -578,27 +633,27 @@ assign rx_doppler_data_valid = rx_doppler_valid;
 // ============================================================================
 // DC NOTCH FILTER (post-Doppler-FFT, pre-CFAR)
 // ============================================================================
-// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
-// sub-frames in the dual 16-pt FFT architecture.
-// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
-//   Sub-frame 0: bins 0-15,  DC = bin 0,  wrap = bin 15
-//   Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
-// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
-// {0,1,15,16,17,31}. etc.
-// When host_dc_notch_width=0: pass-through (no zeroing).
-
-wire dc_notch_active;
-wire [4:0] dop_bin_unsigned = rx_doppler_bin;
-wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
-assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
-                          (bin_within_sf < {1'b0, host_dc_notch_width} ||
-                           bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
+// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
+// sub-frames in the dual 16-pt FFT architecture.
+// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
+//   Sub-frame 0: bins 0-15,  DC = bin 0,  wrap = bin 15
+//   Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
+// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
+// {0,1,15,16,17,31}. etc.
+// When host_dc_notch_width=0: pass-through (no zeroing).
+
+wire dc_notch_active;
+wire [4:0] dop_bin_unsigned = rx_doppler_bin;
+wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
+assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
+                          (bin_within_sf < {1'b0, host_dc_notch_width} ||
+                           bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
 
 // Notched Doppler data: zero I/Q when in notch zone, pass through otherwise
 wire [31:0] notched_doppler_data  = dc_notch_active ? 32'd0 : rx_doppler_output;
 wire        notched_doppler_valid = rx_doppler_valid;
 wire [4:0]  notched_doppler_bin   = rx_doppler_bin;
-wire [5:0]  notched_range_bin     = rx_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0]  notched_range_bin     = rx_range_bin;
 
 // ============================================================================
 // CFAR DETECTOR (replaces simple threshold detector)
@@ -609,7 +664,7 @@ wire [5:0]  notched_range_bin     = rx_range_bin;
 
 wire cfar_detect_flag;
 wire cfar_detect_valid;
-wire [5:0]  cfar_detect_range;
+wire [`RP_RANGE_BIN_BITS-1:0]  cfar_detect_range;
 wire [4:0]  cfar_detect_doppler;
 wire [16:0] cfar_detect_magnitude;
 wire [16:0] cfar_detect_threshold;
@@ -700,9 +755,10 @@ end
 // DATA PACKING FOR USB
 // ============================================================================
 
-// Range profile from matched filter output (wired through radar_receiver_final)
-assign usb_range_profile = rx_range_profile;
-assign usb_range_valid = rx_range_valid;
+// USB range profile must match the advertised 512-bin frame payload, so source it
+// from the decimated range stream that feeds Doppler rather than raw MF samples.
+assign usb_range_profile = {16'd0, rx_range_profile_decimated};
+assign usb_range_valid = rx_range_profile_decimated_valid;
 
 assign usb_doppler_real = rx_doppler_real;
 assign usb_doppler_imag = rx_doppler_imag;
@@ -805,6 +861,11 @@ end else begin : gen_ft2232h
         .cfar_detection(usb_detect_flag),
         .cfar_valid(usb_detect_valid),
 
+        // Bulk frame protocol inputs
+        .range_bin_in(notched_range_bin),
+        .doppler_bin_in(notched_doppler_bin),
+        .frame_complete(rx_frame_complete),
+
         // FT2232H Interface
         .ft_data(ft_data),
         .ft_rxf_n(ft_rxf_n),
@@ -871,6 +932,19 @@ endgenerate
 // we simply sample them in clk_100m when the CDC'd pulse arrives.
 
 // Step 1: Toggle on cmd_valid pulse (ft601_clk domain)
+//
+// CDC INVARIANT (audit F-1.1): usb_cmd_opcode / usb_cmd_addr / usb_cmd_value
+// / usb_cmd_data MUST be driven to their final values BEFORE usb_cmd_valid
+// asserts, and held stable for at least (STAGES + 1) clk_100m cycles after
+// (i.e., until cmd_valid_100m has pulsed in the destination domain). These
+// buses cross from ft601_clk to clk_100m as quasi-static data, NOT through
+// a synchronizer — only the toggle bit above is CDC'd. If a future edit
+// moves the cmd_* register write to the SAME cycle as the toggle flip, or
+// drops the stability hold, the clk_100m sampler at the command decoder
+// will latch metastable bits and dispatch on a garbage opcode.
+// The source-side FSM in usb_data_interface_ft2232h.v / usb_data_interface.v
+// currently satisfies this by assigning the cmd_* buses several cycles
+// before pulsing cmd_valid and leaving them stable until the next command.
 reg cmd_valid_toggle_ft601;
 always @(posedge ft601_clk_buf or negedge sys_reset_ft601_n) begin
     if (!sys_reset_ft601_n)
@@ -913,18 +987,24 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
         host_radar_mode    <= 2'b01;   // Default: auto-scan
         host_trigger_pulse <= 1'b0;
         host_detect_threshold <= 16'd10000; // Default threshold
-        host_stream_control <= 3'b111;    // Default: all streams enabled
+        host_stream_control <= `RP_STREAM_CTRL_DEFAULT; // Default: all streams, mag-only mode
         host_gain_shift     <= 4'd0;      // Default: pass-through (no gain change)
-        // Gap 2: chirp timing defaults (match radar_mode_controller parameters)
-        host_long_chirp_cycles  <= 16'd3000;
-        host_long_listen_cycles <= 16'd13700;
-        host_guard_cycles       <= 16'd17540;
-        host_short_chirp_cycles <= 16'd50;
-        host_short_listen_cycles <= 16'd17450;
+        // Gap 2: chirp timing defaults — initialize pending AND live to the
+        // same default so pre-first-trigger behavior matches the old code.
+        host_long_chirp_cycles_pending   <= 16'd3000;
+        host_long_listen_cycles_pending  <= 16'd13700;
+        host_guard_cycles_pending        <= 16'd17540;
+        host_short_chirp_cycles_pending  <= 16'd50;
+        host_short_listen_cycles_pending <= 16'd17450;
+        host_long_chirp_cycles           <= 16'd3000;
+        host_long_listen_cycles          <= 16'd13700;
+        host_guard_cycles                <= 16'd17540;
+        host_short_chirp_cycles          <= 16'd50;
+        host_short_listen_cycles         <= 16'd17450;
         host_chirps_per_elev    <= 6'd32;
         host_status_request     <= 1'b0;
         chirps_mismatch_error   <= 1'b0;
-        host_range_mode         <= 2'b00;     // Default: auto
+        host_range_mode         <= 2'b00;     // Default: 3 km mode (all short chirps)
         // CFAR defaults (disabled by default — backward-compatible)
         host_cfar_guard         <= 4'd2;      // 2 guard cells each side
         host_cfar_train         <= 5'd8;      // 8 training cells each side
@@ -951,30 +1031,38 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                 8'h01: host_radar_mode     <= usb_cmd_value[1:0];
                 8'h02: host_trigger_pulse  <= 1'b1;
                 8'h03: host_detect_threshold <= usb_cmd_value;
-                8'h04: host_stream_control <= usb_cmd_value[2:0];
-                // Gap 2: chirp timing configuration
-                8'h10: host_long_chirp_cycles  <= usb_cmd_value;
-                8'h11: host_long_listen_cycles <= usb_cmd_value;
-                8'h12: host_guard_cycles       <= usb_cmd_value;
-                8'h13: host_short_chirp_cycles <= usb_cmd_value;
-                8'h14: host_short_listen_cycles <= usb_cmd_value;
+                8'h04: host_stream_control <= usb_cmd_value[5:0];
+                // Gap 2: chirp timing configuration — writes land in the
+                // PENDING set. The live set atomically snapshots pending
+                // on cfg_commit_strobe (S_IDLE or elevation boundary).
+                // See C-4 note at the timing-reg declaration.
+                8'h10: host_long_chirp_cycles_pending   <= usb_cmd_value;
+                8'h11: host_long_listen_cycles_pending  <= usb_cmd_value;
+                8'h12: host_guard_cycles_pending        <= usb_cmd_value;
+                8'h13: host_short_chirp_cycles_pending  <= usb_cmd_value;
+                8'h14: host_short_listen_cycles_pending <= usb_cmd_value;
                 8'h15: begin
-                    // Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
-                    // If host requests a different value, clamp and set error flag.
-                    if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
-                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
-                        chirps_mismatch_error <= 1'b1;
-                    end else if (usb_cmd_value[5:0] == 6'd0) begin
-                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
-                        chirps_mismatch_error <= 1'b1;
-                    end else begin
-                        host_chirps_per_elev  <= usb_cmd_value[5:0];
-                        // Clear error only if value matches FFT size exactly
-                        chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
-                    end
+                    // Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
+                    // If host requests a different value, clamp and set error flag.
+                    if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
+                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
+                        chirps_mismatch_error <= 1'b1;
+                    end else if (usb_cmd_value[5:0] == 6'd0) begin
+                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
+                        chirps_mismatch_error <= 1'b1;
+                    end else begin
+                        host_chirps_per_elev  <= usb_cmd_value[5:0];
+                        // Clear error only if value matches FFT size exactly
+                        chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
+                    end
                 end
                 8'h16: host_gain_shift         <= usb_cmd_value[3:0];  // Fix 3: digital gain
-                8'h20: host_range_mode         <= usb_cmd_value[1:0];  // Fix 7: range mode
+                // Range mode: clamp reserved codes (2'b10, 2'b11) to the safe
+                // 3 km default so a garbled host write cannot silently enable
+                // long-range TX behaviour.
+                8'h20: host_range_mode <= (usb_cmd_value[1:0] > 2'b01)
+                                              ? `RP_RANGE_MODE_3KM
+                                              : usb_cmd_value[1:0];
                 // CFAR configuration opcodes
                 8'h21: host_cfar_guard         <= usb_cmd_value[3:0];
                 8'h22: host_cfar_train         <= usb_cmd_value[4:0];
@@ -998,6 +1086,20 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                 default: ;
             endcase
         end
+
+        // C-4: atomic commit of pending → live timing regs. The strobe is
+        // HIGH while the RX FSM is in S_IDLE and pulses for 1 clk_100m
+        // cycle at every elevation/azimuth boundary. Live regs are only
+        // updated on the strobe, so the FSM always sees a self-consistent
+        // set even when the GUI sends opcodes 0x10..0x14 as separate USB
+        // packets with arbitrary inter-opcode latency.
+        if (cfg_commit_strobe) begin
+            host_long_chirp_cycles   <= host_long_chirp_cycles_pending;
+            host_long_listen_cycles  <= host_long_listen_cycles_pending;
+            host_guard_cycles        <= host_guard_cycles_pending;
+            host_short_chirp_cycles  <= host_short_chirp_cycles_pending;
+            host_short_listen_cycles <= host_short_listen_cycles_pending;
+        end
     end
 end
 
@@ -1040,7 +1142,15 @@ assign system_status = status_reg;
 // DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
 //        tracks the FPGA register as single source of truth.
 // DIG_7: Reserved (tied low for future use).
-assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
+// gpio_dig5: "signal-chain clipped" — asserts on AGC saturation, DDC mixer/FIR
+// overflow, or MTI 2-pulse saturation. Audit F-6.1/F-6.3: these were all
+// previously invisible to the MCU.
+assign gpio_dig5 = (rx_agc_saturation_count != 8'd0)
+                 | rx_ddc_overflow_any
+                 | (rx_ddc_saturation_count != 3'd0)
+                 | (rx_mti_saturation_count != 8'd0)
+                 | rx_range_decim_watchdog    // audit F-6.4
+                 | rx_ddc_cic_fir_overrun;    // audit F-1.2
 assign gpio_dig6 = host_agc_enable;
 assign gpio_dig7 = 1'b0;
 
@@ -1075,4 +1185,4 @@ always @(posedge clk_100m_buf) begin
 end
 `endif
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/radar_system_top_50t.v

@@ -60,6 +60,8 @@ module radar_system_top_50t (
     input wire [7:0] adc_d_n,
     input wire adc_dco_p,
     input wire adc_dco_n,
+    input wire adc_or_p,
+    input wire adc_or_n,
     output wire adc_pwdn,
 
     // ===== STM32 Control (Bank 15: 3.3V) =====
@@ -171,6 +173,8 @@ module radar_system_top_50t (
         .adc_d_n                (adc_d_n),
         .adc_dco_p              (adc_dco_p),
         .adc_dco_n              (adc_dco_n),
+        .adc_or_p               (adc_or_p),
+        .adc_or_n               (adc_or_n),
         .adc_pwdn               (adc_pwdn),
 
         // ----- STM32 Control -----

9_Firmware/9_2_FPGA/radar_transmitter.v

@@ -23,60 +23,65 @@ module radar_transmitter(
     input wire clk_100m,           // System clock
     input wire clk_120m_dac,       // 120MHz DAC clock
     input wire reset_n,            // Reset synchronized to clk_120m_dac
-    input wire reset_100m_n,       // Reset synchronized to clk_100m (for edge detectors/CDC)
-    
-    // DAC Interface
-    output wire [7:0] dac_data,
-    output wire dac_clk,
-    output wire dac_sleep,
-    output wire rx_mixer_en,
+    input wire reset_100m_n,       // Reset synchronized to clk_100m (for edge detectors/CDC)
+    
+    // DAC Interface
+    output wire [7:0] dac_data,
+    output wire dac_clk,
+    output wire dac_sleep,
+    output wire rx_mixer_en,
     output wire tx_mixer_en,
 	 
-	     // STM32 Control Interface
-    input wire stm32_new_chirp,
-    input wire stm32_new_elevation, 
-    input wire stm32_new_azimuth,
+	     // STM32 Control Interface
+    input wire stm32_new_chirp,
+    input wire stm32_new_elevation, 
+    input wire stm32_new_azimuth,
     input wire stm32_mixers_enable,
+
+    // Range mode from host (clk_100m domain, opcode 0x20). CDC'd to clk_120m_dac
+    // internally and fed to plfm_chirp_controller_enhanced so 3 km mode skips
+    // the long-chirp half of the waveform entirely.
+    input wire [1:0] host_range_mode,
 	 
 	 output wire fpga_rf_switch,
 	 
-	     // ADAR1000 Control Interface
-    output wire adar_tx_load_1,
-    output wire adar_rx_load_1,
-    output wire adar_tx_load_2,
-    output wire adar_rx_load_2,
-    output wire adar_tx_load_3,
-    output wire adar_rx_load_3,
-    output wire adar_tx_load_4,
-    output wire adar_rx_load_4,
-    output wire adar_tr_1,
-    output wire adar_tr_2,
-    output wire adar_tr_3,
-    output wire adar_tr_4,
-    
-    // Level Shifter SPI Interface (STM32F7 to ADAR1000)
-    input wire stm32_sclk_3v3,
-    input wire stm32_mosi_3v3,
-    output wire stm32_miso_3v3,
-    input wire stm32_cs_adar1_3v3,
-    input wire stm32_cs_adar2_3v3,
-    input wire stm32_cs_adar3_3v3,
-    input wire stm32_cs_adar4_3v3,
-    
-    output wire stm32_sclk_1v8,
-    output wire stm32_mosi_1v8,
-    input wire stm32_miso_1v8,
-    output wire stm32_cs_adar1_1v8,
-    output wire stm32_cs_adar2_1v8,
-    output wire stm32_cs_adar3_1v8,
+	     // ADAR1000 Control Interface
+    output wire adar_tx_load_1,
+    output wire adar_rx_load_1,
+    output wire adar_tx_load_2,
+    output wire adar_rx_load_2,
+    output wire adar_tx_load_3,
+    output wire adar_rx_load_3,
+    output wire adar_tx_load_4,
+    output wire adar_rx_load_4,
+    output wire adar_tr_1,
+    output wire adar_tr_2,
+    output wire adar_tr_3,
+    output wire adar_tr_4,
+    
+    // Level Shifter SPI Interface (STM32F7 to ADAR1000)
+    input wire stm32_sclk_3v3,
+    input wire stm32_mosi_3v3,
+    output wire stm32_miso_3v3,
+    input wire stm32_cs_adar1_3v3,
+    input wire stm32_cs_adar2_3v3,
+    input wire stm32_cs_adar3_3v3,
+    input wire stm32_cs_adar4_3v3,
+    
+    output wire stm32_sclk_1v8,
+    output wire stm32_mosi_1v8,
+    input wire stm32_miso_1v8,
+    output wire stm32_cs_adar1_1v8,
+    output wire stm32_cs_adar2_1v8,
+    output wire stm32_cs_adar3_1v8,
     output wire stm32_cs_adar4_1v8,
 	 
-			 // Beam Position Tracking
-	 output wire [5:0] current_elevation,
-	 output wire [5:0] current_azimuth,
+			 // Beam Position Tracking
+	 output wire [5:0] current_elevation,
+	 output wire [5:0] current_azimuth,
 	 output wire [5:0] current_chirp,
-	 output wire new_chirp_frame
-
+	 output wire new_chirp_frame
+
 
     );
 	 
@@ -143,6 +148,26 @@ always @(posedge clk_120m_dac or negedge reset_n) begin
 end
 assign new_chirp_pulse_120m = chirp_toggle_120m ^ chirp_toggle_120m_prev;
 
+// Sync host_range_mode (clk_100m level) to clk_120m_dac domain.
+// Only bit[0] toggles between the two valid codes (2'b00 / 2'b01) since
+// reserved codes are clamped at the source, so per-bit 2FF synchronization
+// has no coherency hazard.
+wire [1:0] range_mode_120m;
+cdc_single_bit #(.STAGES(2)) cdc_range_mode_bit0 (
+    .src_clk(clk_100m),
+    .dst_clk(clk_120m_dac),
+    .reset_n(reset_n),
+    .src_signal(host_range_mode[0]),
+    .dst_signal(range_mode_120m[0])
+);
+cdc_single_bit #(.STAGES(2)) cdc_range_mode_bit1 (
+    .src_clk(clk_100m),
+    .dst_clk(clk_120m_dac),
+    .reset_n(reset_n),
+    .src_signal(host_range_mode[1]),
+    .dst_signal(range_mode_120m[1])
+);
+
 // Sync stm32_mixers_enable (async GPIO level) to clk_120m_dac domain
 cdc_single_bit #(.STAGES(3)) cdc_mixers_en_120m (
     .src_clk(clk_100m),         // Treat as pseudo-source (GPIO is async)
@@ -150,7 +175,7 @@ cdc_single_bit #(.STAGES(3)) cdc_mixers_en_120m (
     .reset_n(reset_n),
     .src_signal(stm32_mixers_enable),
     .dst_signal(mixers_enable_120m)
-);
+);
 
 // CDC synchronizers: async STM32 GPIO inputs -> clk_100m domain
 // These prevent metastability in the edge detectors. Without these,
@@ -201,7 +226,7 @@ edge_detector_enhanced azimuth_edge (
     .reset_n(reset_100m_n),
     .signal_in(stm32_new_azimuth_sync),
     .rising_falling_edge(new_azimuth_pulse)
-);
+);
 
 // Enhanced PLFM Chirp Generation
 plfm_chirp_controller_enhanced plfm_chirp_inst (
@@ -212,38 +237,39 @@ plfm_chirp_controller_enhanced plfm_chirp_inst (
     .new_elevation(new_elevation_pulse),
     .new_azimuth(new_azimuth_pulse),
     .new_chirp_frame(new_chirp_frame),
-    .mixers_enable(mixers_enable_120m),    // CDC-synchronized level in clk_120m domain
-    .chirp_data(chirp_data),
-    .chirp_valid(chirp_valid),
-    .chirp_done(chirp_sequence_done),
-    .rf_switch_ctrl(fpga_rf_switch),
-    .rx_mixer_en(rx_mixer_en),
-    .tx_mixer_en(tx_mixer_en),
-    .adar_tx_load_1(adar_tx_load_1),
-    .adar_rx_load_1(adar_rx_load_1),
-    .adar_tx_load_2(adar_tx_load_2),
-    .adar_rx_load_2(adar_rx_load_2),
-    .adar_tx_load_3(adar_tx_load_3),
-    .adar_rx_load_3(adar_rx_load_3),
-    .adar_tx_load_4(adar_tx_load_4),
-    .adar_rx_load_4(adar_rx_load_4),
-    .adar_tr_1(adar_tr_1),
-    .adar_tr_2(adar_tr_2),
-    .adar_tr_3(adar_tr_3),
-    .adar_tr_4(adar_tr_4),
-    .elevation_counter(current_elevation),
-    .azimuth_counter(current_azimuth),
-    .chirp_counter(current_chirp)
+    .mixers_enable(mixers_enable_120m),    // CDC-synchronized level in clk_120m domain
+    .range_mode(range_mode_120m),          // CDC-synchronized range mode in clk_120m domain
+    .chirp_data(chirp_data),
+    .chirp_valid(chirp_valid),
+    .chirp_done(chirp_sequence_done),
+    .rf_switch_ctrl(fpga_rf_switch),
+    .rx_mixer_en(rx_mixer_en),
+    .tx_mixer_en(tx_mixer_en),
+    .adar_tx_load_1(adar_tx_load_1),
+    .adar_rx_load_1(adar_rx_load_1),
+    .adar_tx_load_2(adar_tx_load_2),
+    .adar_rx_load_2(adar_rx_load_2),
+    .adar_tx_load_3(adar_tx_load_3),
+    .adar_rx_load_3(adar_rx_load_3),
+    .adar_tx_load_4(adar_tx_load_4),
+    .adar_rx_load_4(adar_rx_load_4),
+    .adar_tr_1(adar_tr_1),
+    .adar_tr_2(adar_tr_2),
+    .adar_tr_3(adar_tr_3),
+    .adar_tr_4(adar_tr_4),
+    .elevation_counter(current_elevation),
+    .azimuth_counter(current_azimuth),
+    .chirp_counter(current_chirp)
 );
 
-// Enhanced DAC Interface
-dac_interface_enhanced dac_interface_inst (
-    .clk_120m(clk_120m_dac),
-    .reset_n(reset_n),
-    .chirp_data(chirp_data),
-    .chirp_valid(chirp_valid),
-    .dac_data(dac_data),
-    .dac_clk(dac_clk),
-    .dac_sleep(dac_sleep)
+// Enhanced DAC Interface
+dac_interface_enhanced dac_interface_inst (
+    .clk_120m(clk_120m_dac),
+    .reset_n(reset_n),
+    .chirp_data(chirp_data),
+    .chirp_valid(chirp_valid),
+    .dac_data(dac_data),
+    .dac_clk(dac_clk),
+    .dac_sleep(dac_sleep)
 );
 endmodule

9_Firmware/9_2_FPGA/range_bin_decimator.v

@@ -3,7 +3,7 @@
 /**
  * range_bin_decimator.v
  *
- * Reduces 1024 range bins from the matched filter output down to 64 bins
+ * Reduces 2048 range bins from the matched filter output down to 512 bins
  * for the Doppler processor. Supports multiple decimation modes:
  *
  *   Mode 2'b00: Simple decimation (take every Nth sample)
@@ -11,29 +11,31 @@
  *   Mode 2'b10: Averaging (sum group and divide by N)
  *   Mode 2'b11: Reserved
  *
- * Interface contract (from radar_receiver_final.v line 229):
+ * Interface contract (from radar_receiver_final.v):
  *   .clk, .reset_n
- *   .range_i_in, .range_q_in, .range_valid_in   ← from matched_filter output
- *   .range_i_out, .range_q_out, .range_valid_out → to Doppler processor
- *   .range_bin_index                             → 6-bit output bin index
- *   .decimation_mode                             ← 2-bit mode select
- *   .start_bin                                   ← 10-bit start offset
+ *   .range_i_in, .range_q_in, .range_valid_in   <- from matched_filter output
+ *   .range_i_out, .range_q_out, .range_valid_out -> to Doppler processor
+ *   .range_bin_index                             -> 9-bit output bin index
+ *   .decimation_mode                             <- 2-bit mode select
+ *   .start_bin                                   <- 11-bit start offset
  *
  * start_bin usage:
  *   When start_bin > 0, the decimator skips the first 'start_bin' valid
  *   input samples before beginning decimation. This allows selecting a
- *   region of interest within the 1024 range bins (e.g., to focus on
+ *   region of interest within the 2048 range bins (e.g., to focus on
  *   near-range or far-range targets). When start_bin = 0 (default),
- *   all 1024 bins are processed starting from bin 0.
+ *   all 2048 bins are processed starting from bin 0.
  *
  * Clock domain: clk (100 MHz)
- * Decimation: 1024 → 64 (factor of 16)
+ * Decimation: 2048 -> 512 (factor of 4)
  */
 
+`include "radar_params.vh"
+
 module range_bin_decimator #(
-    parameter INPUT_BINS        = 1024,
-    parameter OUTPUT_BINS       = 64,
-    parameter DECIMATION_FACTOR = 16
+    parameter INPUT_BINS        = `RP_FFT_SIZE,          // 2048
+    parameter OUTPUT_BINS       = `RP_NUM_RANGE_BINS,    // 512
+    parameter DECIMATION_FACTOR = `RP_DECIMATION_FACTOR  // 4
 ) (
     input wire clk,
     input wire reset_n,
@@ -47,11 +49,11 @@ module range_bin_decimator #(
     output reg signed [15:0] range_i_out,
     output reg signed [15:0] range_q_out,
     output reg range_valid_out,
-    output reg [5:0] range_bin_index,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_index,  // 9-bit
 
     // Configuration
     input wire [1:0] decimation_mode,  // 00=decimate, 01=peak, 10=average
-    input wire [9:0] start_bin,        // First input bin to process
+    input wire [10:0] start_bin,       // First input bin to process (11-bit for 2048)
 
     // Diagnostics
     output reg watchdog_timeout        // Pulses high for 1 cycle on watchdog reset
@@ -59,10 +61,10 @@ module range_bin_decimator #(
 `ifdef FORMAL
     ,
     output wire [2:0]  fv_state,
-    output wire [9:0]  fv_in_bin_count,
-    output wire [3:0]  fv_group_sample_count,
-    output wire [5:0]  fv_output_bin_count,
-    output wire [9:0]  fv_skip_count
+    output wire [10:0] fv_in_bin_count,
+    output wire [1:0]  fv_group_sample_count,
+    output wire [8:0]  fv_output_bin_count,
+    output wire [10:0] fv_skip_count
 `endif
 );
 
@@ -75,12 +77,12 @@ localparam WATCHDOG_LIMIT = 10'd256;
 // INTERNAL SIGNALS
 // ============================================================================
 
-// Input bin counter (0..1023)
-reg [9:0] in_bin_count;
+// Input bin counter (0..2047)
+reg [10:0] in_bin_count;
 
 // Group tracking
-reg [3:0] group_sample_count;  // 0..15 within current group of 16
-reg [5:0] output_bin_count;    // 0..63 output bin index
+reg [1:0] group_sample_count;   // 0..3 within current group of 4
+reg [8:0] output_bin_count;     // 0..511 output bin index
 
 // State machine
 reg [2:0] state;
@@ -91,7 +93,7 @@ localparam ST_EMIT    = 3'd3;
 localparam ST_DONE    = 3'd4;
 
 // Skip counter for start_bin
-reg [9:0] skip_count;
+reg [10:0] skip_count;
 
 // Watchdog counter — counts consecutive clocks with no range_valid_in
 reg [9:0] watchdog_count;
@@ -107,7 +109,7 @@ assign fv_skip_count         = skip_count;
 // ============================================================================
 // PEAK DETECTION (Mode 01)
 // ============================================================================
-// Track the sample with the largest magnitude in the current group of 16
+// Track the sample with the largest magnitude in the current group of 4
 reg signed [15:0] peak_i, peak_q;
 reg [16:0] peak_mag;  // |I| + |Q| approximation
 wire [16:0] cur_mag;
@@ -120,8 +122,8 @@ assign cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 // ============================================================================
 // AVERAGING (Mode 10)
 // ============================================================================
-// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>4)
-reg signed [19:0] sum_i, sum_q;  // 16 + 4 guard bits for sum of 16 values
+// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>2)
+reg signed [17:0] sum_i, sum_q;  // 16 + 2 guard bits for sum of 4 values
 
 // ============================================================================
 // SIMPLE DECIMATION (Mode 00)
@@ -135,21 +137,21 @@ reg signed [15:0] decim_i, decim_q;
 always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         state             <= ST_IDLE;
-        in_bin_count      <= 10'd0;
-        group_sample_count <= 4'd0;
-        output_bin_count  <= 6'd0;
-        skip_count        <= 10'd0;
+        in_bin_count      <= 11'd0;
+        group_sample_count <= 2'd0;
+        output_bin_count  <= 9'd0;
+        skip_count        <= 11'd0;
         watchdog_count    <= 10'd0;
         watchdog_timeout  <= 1'b0;
         range_valid_out   <= 1'b0;
         range_i_out       <= 16'd0;
         range_q_out       <= 16'd0;
-        range_bin_index   <= 6'd0;
+        range_bin_index   <= {`RP_RANGE_BIN_BITS{1'b0}};
         peak_i            <= 16'd0;
         peak_q            <= 16'd0;
         peak_mag          <= 17'd0;
-        sum_i             <= 20'd0;
-        sum_q             <= 20'd0;
+        sum_i             <= 18'd0;
+        sum_q             <= 18'd0;
         decim_i           <= 16'd0;
         decim_q           <= 16'd0;
     end else begin
@@ -162,33 +164,33 @@ always @(posedge clk or negedge reset_n) begin
         // IDLE: Wait for first valid input
         // ================================================================
         ST_IDLE: begin
-            in_bin_count       <= 10'd0;
-            group_sample_count <= 4'd0;
-            output_bin_count   <= 6'd0;
-            skip_count         <= 10'd0;
+            in_bin_count       <= 11'd0;
+            group_sample_count <= 2'd0;
+            output_bin_count   <= 9'd0;
+            skip_count         <= 11'd0;
             watchdog_count     <= 10'd0;
             peak_i             <= 16'd0;
             peak_q             <= 16'd0;
             peak_mag           <= 17'd0;
-            sum_i              <= 20'd0;
-            sum_q              <= 20'd0;
+            sum_i              <= 18'd0;
+            sum_q              <= 18'd0;
 
             if (range_valid_in) begin
-                in_bin_count <= 10'd1;
+                in_bin_count <= 11'd1;
 
-                if (start_bin > 10'd0) begin
+                if (start_bin > 11'd0) begin
                     // Need to skip 'start_bin' samples first
-                    skip_count <= 10'd1;
+                    skip_count <= 11'd1;
                     state      <= ST_SKIP;
                 end else begin
                     // No skip — process first sample immediately
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
 
                     // Mode-specific first sample handling
                     case (decimation_mode)
                     2'b00: begin  // Simple decimation — check if center sample
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -199,8 +201,8 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin  // Averaging
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
@@ -219,11 +221,11 @@ always @(posedge clk or negedge reset_n) begin
                 if (skip_count >= start_bin) begin
                     // Done skipping — this sample is the first to process
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
 
                     case (decimation_mode)
                     2'b00: begin
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -234,8 +236,8 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
@@ -281,8 +283,8 @@ always @(posedge clk or negedge reset_n) begin
                     end
                 end
                 2'b10: begin  // Averaging
-                    sum_i <= sum_i + {{4{range_i_in[15]}}, range_i_in};
-                    sum_q <= sum_q + {{4{range_q_in[15]}}, range_q_in};
+                    sum_i <= sum_i + {{2{range_i_in[15]}}, range_i_in};
+                    sum_q <= sum_q + {{2{range_q_in[15]}}, range_q_in};
                 end
                 default: ;
                 endcase
@@ -291,7 +293,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (group_sample_count == DECIMATION_FACTOR - 1) begin
                     // Group complete — emit output
                     state <= ST_EMIT;
-                    group_sample_count <= 4'd0;
+                    group_sample_count <= 2'd0;
                 end else if (in_bin_count >= INPUT_BINS - 1) begin
                     // Overflow guard: consumed all input bins but group
                     // is not yet complete. Stop to prevent corruption of
@@ -331,9 +333,9 @@ always @(posedge clk or negedge reset_n) begin
                 range_i_out <= peak_i;
                 range_q_out <= peak_q;
             end
-            2'b10: begin  // Averaging (sum >> 4 = divide by 16)
-                range_i_out <= sum_i[19:4];
-                range_q_out <= sum_q[19:4];
+            2'b10: begin  // Averaging (sum >> 2 = divide by 4)
+                range_i_out <= sum_i[17:2];
+                range_q_out <= sum_q[17:2];
             end
             default: begin
                 range_i_out <= 16'd0;
@@ -345,8 +347,8 @@ always @(posedge clk or negedge reset_n) begin
             peak_i   <= 16'd0;
             peak_q   <= 16'd0;
             peak_mag <= 17'd0;
-            sum_i    <= 20'd0;
-            sum_q    <= 20'd0;
+            sum_i    <= 18'd0;
+            sum_q    <= 18'd0;
 
             // Advance output bin
             output_bin_count <= output_bin_count + 1;
@@ -358,12 +360,12 @@ always @(posedge clk or negedge reset_n) begin
                 // If we already have valid input waiting, process it immediately
                 if (range_valid_in) begin
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
                     in_bin_count       <= in_bin_count + 1;
 
                     case (decimation_mode)
                     2'b00: begin
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -374,20 +376,20 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
                 end else begin
                     state <= ST_PROCESS;
-                    group_sample_count <= 4'd0;
+                    group_sample_count <= 2'd0;
                 end
             end
         end
 
         // ================================================================
-        // DONE: All 64 output bins emitted, return to idle
+        // DONE: All 512 output bins emitted, return to idle
         // ================================================================
         ST_DONE: begin
             state <= ST_IDLE;

9_Firmware/9_2_FPGA/run_regression.sh

@@ -264,11 +264,141 @@ run_lint_static() {
     fi
 }
 
+# ---------------------------------------------------------------------------
+# Helper: compile, run, and compare a matched-filter co-sim scenario
+#   run_mf_cosim <scenario_name> <define_flag>
+# ---------------------------------------------------------------------------
+run_mf_cosim() {
+    local name="$1"
+    local define="$2"
+    local vvp="tb/tb_mf_cosim_${name}.vvp"
+    local scenario_lower="$name"
+
+    printf "  %-45s " "MF Co-Sim ($name)"
+
+    # Compile — build command as string to handle optional define
+    local cmd="iverilog -g2001 -DSIMULATION"
+    if [[ -n "$define" ]]; then
+        cmd="$cmd $define"
+    fi
+    cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
+
+    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
+        echo -e "${RED}COMPILE FAIL${NC}"
+        ERRORS="$ERRORS\n  MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run TB
+    local output
+    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    rm -f "$vvp"
+
+    # Check TB internal pass/fail
+    local tb_fail
+    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
+    if [[ "$tb_fail" -gt 0 ]]; then
+        echo -e "${RED}FAIL${NC} (TB internal failure)"
+        ERRORS="$ERRORS\n  MF Co-Sim ($name): TB internal failure"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run Python compare
+    if command -v python3 >/dev/null 2>&1; then
+        local compare_out
+        local compare_rc=0
+        compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
+        if [[ "$compare_rc" -ne 0 ]]; then
+            echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
+            ERRORS="$ERRORS\n  MF Co-Sim ($name): Python compare failed"
+            FAIL=$((FAIL + 1))
+            return
+        fi
+    else
+        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
+        SKIP=$((SKIP + 1))
+        return
+    fi
+
+    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
+    PASS=$((PASS + 1))
+}
+
+# ---------------------------------------------------------------------------
+# Helper: compile, run, and compare a Doppler co-sim scenario
+#   run_doppler_cosim <scenario_name> <define_flag>
+# ---------------------------------------------------------------------------
+run_doppler_cosim() {
+    local name="$1"
+    local define="$2"
+    local vvp="tb/tb_doppler_cosim_${name}.vvp"
+
+    printf "  %-45s " "Doppler Co-Sim ($name)"
+
+    # Compile — build command as string to handle optional define
+    local cmd="iverilog -g2001 -DSIMULATION"
+    if [[ -n "$define" ]]; then
+        cmd="$cmd $define"
+    fi
+    cmd="$cmd -o $vvp tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v"
+
+    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
+        echo -e "${RED}COMPILE FAIL${NC}"
+        ERRORS="$ERRORS\n  Doppler Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run TB
+    local output
+    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    rm -f "$vvp"
+
+    # Check TB internal pass/fail
+    local tb_fail
+    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
+    if [[ "$tb_fail" -gt 0 ]]; then
+        echo -e "${RED}FAIL${NC} (TB internal failure)"
+        ERRORS="$ERRORS\n  Doppler Co-Sim ($name): TB internal failure"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run Python compare
+    if command -v python3 >/dev/null 2>&1; then
+        local compare_out
+        local compare_rc=0
+        compare_out=$(python3 tb/cosim/compare_doppler.py "$name" 2>&1) || compare_rc=$?
+        if [[ "$compare_rc" -ne 0 ]]; then
+            echo -e "${RED}FAIL${NC} (compare_doppler.py mismatch)"
+            ERRORS="$ERRORS\n  Doppler Co-Sim ($name): Python compare failed"
+            FAIL=$((FAIL + 1))
+            return
+        fi
+    else
+        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
+        SKIP=$((SKIP + 1))
+        return
+    fi
+
+    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
+    PASS=$((PASS + 1))
+}
+
 # ---------------------------------------------------------------------------
 # Helper: compile and run a single testbench
 #   run_test <name> <vvp_path> <iverilog_args...>
 # ---------------------------------------------------------------------------
 run_test() {
+    # Optional: --timeout=N as first arg overrides default 120s
+    local timeout_secs=120
+    if [[ "$1" == --timeout=* ]]; then
+        timeout_secs="${1#--timeout=}"
+        shift
+    fi
+
     local name="$1"
     local vvp="$2"
     shift 2
@@ -286,7 +416,7 @@ run_test() {
 
     # Run
     local output
-    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    output=$(timeout "$timeout_secs" vvp "$vvp" 2>&1) || true
 
     # Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
     local test_pass test_fail
@@ -378,9 +508,9 @@ run_test "Chirp Contract" \
     tb/tb_chirp_ctr_reg.vvp \
     tb/tb_chirp_contract.v plfm_chirp_controller.v
 
-run_test "Doppler Processor (DSP48)" \
-    tb/tb_doppler_reg.vvp \
-    tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v
+run_doppler_cosim "stationary"   ""
+run_doppler_cosim "moving"       "-DSCENARIO_MOVING"
+run_doppler_cosim "two_targets"  "-DSCENARIO_TWO"
 
 run_test "Threshold Detector (detection bugs)" \
     tb/tb_threshold_detector.vvp \
@@ -427,15 +557,16 @@ run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
     doppler_processor.v xfft_16.v fft_engine.v
 
 if [[ "$QUICK" -eq 0 ]]; then
-    # Golden generate
-    run_test "Receiver (golden generate)" \
-        tb/tb_rx_golden_reg.vvp \
-        -DGOLDEN_GENERATE \
-        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
-
-    # Golden compare
-    run_test "Receiver (golden compare)" \
-        tb/tb_rx_compare_reg.vvp \
+    # Receiver integration (structural + bounds + pulse assertions).
+    # Replaces the earlier "Receiver golden generate/compare" pair, which was
+    # self-blessing (both passes ran identical RTL on identical stimulus, so
+    # it passed regardless of bugs). Real co-sim coverage is now provided by
+    # tb_doppler_realdata.v and tb_fullchain_realdata.v (Python goldens,
+    # exact match); this integration test exercises the full RX pipeline
+    # (ADC stub → DDC → MF → Decim → Doppler) and verifies that
+    # doppler_frame_done is a single-cycle pulse at module boundaries.
+    run_test --timeout=600 "Receiver Integration (tb_radar_receiver_final)" \
+        tb/tb_rx_final_reg.vvp \
         tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
 
     # Full system top (monitoring-only, legacy)
@@ -459,12 +590,28 @@ if [[ "$QUICK" -eq 0 ]]; then
         -DUSB_MODE_1 \
         tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
 else
-    echo "  (skipped receiver golden + system top + E2E — use without --quick)"
-    SKIP=$((SKIP + 6))
+    echo "  (skipped receiver integration + system top + E2E + USB_MODE=1 variants — use without --quick)"
+    SKIP=$((SKIP + 5))
 fi
 
 echo ""
 
+# ===========================================================================
+# PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
+# Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
+# against committed Python golden CSV files. In SIMULATION mode, thresholds
+# are generous (behavioral vs fixed-point twiddles differ) — validates
+# state machine mechanics, output count, and energy sanity.
+# ===========================================================================
+echo "--- PHASE 2b: Matched Filter Co-Sim ---"
+
+run_mf_cosim "chirp"   ""
+run_mf_cosim "dc"      "-DSCENARIO_DC"
+run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
+run_mf_cosim "tone5"   "-DSCENARIO_TONE5"
+
+echo ""
+
 # ===========================================================================
 # PHASE 3: UNIT TESTS — Signal Processing
 # ===========================================================================

9_Firmware/9_2_FPGA/rx_gain_control.v

@@ -54,7 +54,7 @@ module rx_gain_control (
     input  wire [3:0]  agc_decay,      // 0x2B: amplification step when weak (default 1)
     input  wire [3:0]  agc_holdoff,    // 0x2C: frames to wait before gain-up (default 4)
 
-    // Frame boundary pulse (1 clk cycle, from Doppler frame_complete)
+    // Frame boundary pulse (1 clk cycle, from edge detector in radar_receiver_final)
     input  wire        frame_boundary,
 
     // Data output (to matched filter)

9_Firmware/9_2_FPGA/tb/ad9484_interface_400m_stub.v

@@ -19,6 +19,10 @@ module ad9484_interface_400m (
     input wire [7:0] adc_d_n,
     input wire adc_dco_p,
     input wire adc_dco_n,
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair — stub treats adc_or_p as
+    // the single-ended overrange flag, adc_or_n is ignored.
+    input wire adc_or_p,
+    input wire adc_or_n,
 
     // System Interface
     input wire sys_clk,
@@ -27,7 +31,8 @@ module ad9484_interface_400m (
     // Output at 400MHz domain
     output wire [7:0] adc_data_400m,
     output wire adc_data_valid_400m,
-    output wire adc_dco_bufg
+    output wire adc_dco_bufg,
+    output wire adc_overrange_400m
 );
 
 // Pass-through clock (no BUFG needed in simulation)
@@ -50,4 +55,15 @@ end
 assign adc_data_400m = adc_data_400m_reg;
 assign adc_data_valid_400m = adc_data_valid_400m_reg;
 
+// Audit F-0.1: 1-cycle pipeline of adc_or_p to match the real IDDR+register
+// capture path. TB drives adc_or_p directly with the overrange flag.
+reg adc_overrange_400m_reg;
+always @(posedge adc_dco_p or negedge reset_n) begin
+    if (!reset_n)
+        adc_overrange_400m_reg <= 1'b0;
+    else
+        adc_overrange_400m_reg <= adc_or_p;
+end
+assign adc_overrange_400m = adc_overrange_400m_reg;
+
 endmodule

9_Firmware/9_2_FPGA/tb/cosim/compare_doppler.py

@@ -34,8 +34,8 @@ sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 # =============================================================================
 
 DOPPLER_FFT = 32
-RANGE_BINS = 64
-TOTAL_OUTPUTS = RANGE_BINS * DOPPLER_FFT  # 2048
+RANGE_BINS = 512
+TOTAL_OUTPUTS = RANGE_BINS * DOPPLER_FFT  # 16384
 SUBFRAME_SIZE = 16
 
 SCENARIOS = {
@@ -246,7 +246,7 @@ def compare_scenario(name, config, base_dir):
     # ---- Pass/Fail ----
     checks = []
 
-    checks.append(('RTL output count == 2048', count_ok))
+    checks.append(('RTL output count == 16384', count_ok))
 
     energy_ok = (ENERGY_RATIO_MIN < energy_ratio < ENERGY_RATIO_MAX)
     checks.append((f'Energy ratio in bounds '

9_Firmware/9_2_FPGA/tb/cosim/compare_mf.py

@@ -36,7 +36,7 @@ sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 # Configuration
 # =============================================================================
 
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 
 SCENARIOS = {
     'chirp': {
@@ -243,7 +243,7 @@ def compare_scenario(scenario_name, config, base_dir):
 
     # Check 2: RTL produced expected sample count
     correct_count = len(rtl_i) == FFT_SIZE
-    checks.append(('Correct output count (1024)', correct_count))
+    checks.append(('Correct output count (2048)', correct_count))
 
     # Check 3: Energy ratio within generous bounds
     # Allow very wide range since twiddle differences cause large gain variation

9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py

@@ -291,12 +291,9 @@ class Mixer:
         Convert 8-bit unsigned ADC to 18-bit signed.
         RTL: adc_signed_w = {1'b0, adc_data, {9{1'b0}}} -
                             {1'b0, {8{1'b1}}, {9{1'b0}}} / 2
-
-        Verilog '/' binds tighter than '-', so the division applies
-        only to the second concatenation:
-            {1'b0, 8'hFF, 9'b0} = 0x1FE00
-            0x1FE00 / 2 = 0xFF00 = 65280
-        Result: (adc_data << 9) - 0xFF00
+        = (adc_data << 9) - (0xFF << 9) / 2
+        = (adc_data << 9) - (0xFF << 8)  [integer division]
+        = (adc_data << 9) - 0x7F80
         """
         adc_data_8bit = adc_data_8bit & 0xFF
         # {1'b0, adc_data, 9'b0} = adc_data << 9, zero-padded to 18 bits
@@ -712,15 +709,24 @@ class DDCInputInterface:
 # FFT Engine (1024-point radix-2 DIT, in-place, 32-bit internal)
 # =============================================================================
 
-def load_twiddle_rom(filepath=None):
+def load_twiddle_rom(filepath=None, n=2048):
     """
-    Load 256-entry quarter-wave cosine ROM from hex file.
-    Returns list of 256 signed 16-bit integers.
+    Load quarter-wave cosine ROM from hex file.
+    Returns list of N/4 signed 16-bit integers.
+
+    For N=2048: loads fft_twiddle_2048.mem (512 entries).
+    For N=1024: loads fft_twiddle_1024.mem (256 entries).
+    For N=16:   loads fft_twiddle_16.mem (4 entries).
     """
     if filepath is None:
         # Default path relative to this file
         base = os.path.dirname(os.path.abspath(__file__))
-        filepath = os.path.join(base, '..', '..', 'fft_twiddle_1024.mem')
+        if n == 2048:
+            filepath = os.path.join(base, '..', '..', 'fft_twiddle_2048.mem')
+        elif n == 16:
+            filepath = os.path.join(base, '..', '..', 'fft_twiddle_16.mem')
+        else:
+            filepath = os.path.join(base, '..', '..', 'fft_twiddle_1024.mem')
 
     values = []
     with open(filepath) as f:
@@ -762,17 +768,17 @@ class FFTEngine:
     """
     Bit-accurate model of fft_engine.v
 
-    1024-point radix-2 DIT FFT/IFFT.
+    2048-point radix-2 DIT FFT/IFFT.
     Internal: 32-bit signed working data.
     Twiddle: 16-bit Q15 from quarter-wave cosine ROM.
     Butterfly: multiply 32x16->49 bits, >>>15, add/subtract.
     Output: saturate 32->16 bits. IFFT also >>>LOG2N before saturate.
     """
 
-    def __init__(self, n=1024, twiddle_file=None):
+    def __init__(self, n=2048, twiddle_file=None):
         self.N = n
         self.LOG2N = n.bit_length() - 1
-        self.cos_rom = load_twiddle_rom(twiddle_file)
+        self.cos_rom = load_twiddle_rom(twiddle_file, n=n)
         # Working memory (32-bit signed I/Q pairs)
         self.mem_re = [0] * n
         self.mem_im = [0] * n
@@ -945,21 +951,21 @@ class MatchedFilterChain:
     Uses a single FFTEngine instance (as in RTL, engine is reused).
     """
 
-    def __init__(self, fft_size=1024, twiddle_file=None):
+    def __init__(self, fft_size=2048, twiddle_file=None):
         self.fft_size = fft_size
         self.fft = FFTEngine(n=fft_size, twiddle_file=twiddle_file)
         self.conj_mult = FreqMatchedFilter()
 
     def process(self, sig_re, sig_im, ref_re, ref_im):
         """
-        Run matched filter on 1024-sample signal + reference.
+        Run matched filter on signal + reference.
 
         Args:
-            sig_re/im: signal I/Q (16-bit signed, 1024 samples)
-            ref_re/im: reference chirp I/Q (16-bit signed, 1024 samples)
+            sig_re/im: signal I/Q (16-bit signed, fft_size samples)
+            ref_re/im: reference chirp I/Q (16-bit signed, fft_size samples)
 
         Returns:
-            (range_profile_re, range_profile_im): 1024 x 16-bit signed
+            (range_profile_re, range_profile_im): fft_size x 16-bit signed
         """
         # Forward FFT of signal
         sig_fft_re, sig_fft_im = self.fft.compute(sig_re, sig_im, inverse=False)
@@ -987,27 +993,27 @@ class RangeBinDecimator:
     Bit-accurate model of range_bin_decimator.v
 
     Three modes:
-      00: Simple decimation (take center sample at index 8)
+      00: Simple decimation (take center sample at index 2)
       01: Peak detection (max |I|+|Q|)
-      10: Averaging (sum >> 4, truncation)
+      10: Averaging (sum >> 2, truncation)
       11: Reserved (output 0)
     """
 
-    DECIMATION_FACTOR = 16
-    OUTPUT_BINS = 64
+    DECIMATION_FACTOR = 4
+    OUTPUT_BINS = 512
 
     @staticmethod
     def decimate(range_re, range_im, mode=1, start_bin=0):
         """
-        Decimate 1024 range bins to 64.
+        Decimate 2048 range bins to 512.
 
         Args:
-            range_re/im: 1024 x signed 16-bit
+            range_re/im: 2048 x signed 16-bit
             mode: 0=center, 1=peak, 2=average, 3=zero
-            start_bin: first input bin to process (0-1023)
+            start_bin: first input bin to process (0-2047)
 
         Returns:
-            (out_re, out_im): 64 x signed 16-bit
+            (out_re, out_im): 512 x signed 16-bit
         """
         out_re = []
         out_im = []
@@ -1055,9 +1061,9 @@ class RangeBinDecimator:
                     if idx < len(range_re):
                         sum_re += sign_extend(range_re[idx] & 0xFFFF, 16)
                         sum_im += sign_extend(range_im[idx] & 0xFFFF, 16)
-                # Truncate (arithmetic right shift by 4), take 16 bits
-                out_re.append(sign_extend((sum_re >> 4) & 0xFFFF, 16))
-                out_im.append(sign_extend((sum_im >> 4) & 0xFFFF, 16))
+                # Truncate (arithmetic right shift by 2), take 16 bits
+                out_re.append(sign_extend((sum_re >> 2) & 0xFFFF, 16))
+                out_im.append(sign_extend((sum_im >> 2) & 0xFFFF, 16))
 
             else:
                 # Mode 3: reserved, output 0
@@ -1093,7 +1099,7 @@ class DopplerProcessor:
     """
 
     DOPPLER_FFT_SIZE = 16     # Per sub-frame
-    RANGE_BINS = 64
+    RANGE_BINS = 512
     CHIRPS_PER_FRAME = 32
     CHIRPS_PER_SUBFRAME = 16
 
@@ -1129,11 +1135,11 @@ class DopplerProcessor:
         Process one complete Doppler frame using dual 16-pt FFTs.
 
         Args:
-            chirp_data_i: 2D array [32 chirps][64 range bins] of signed 16-bit I
-            chirp_data_q: 2D array [32 chirps][64 range bins] of signed 16-bit Q
+            chirp_data_i: 2D array [32 chirps][512 range bins] of signed 16-bit I
+            chirp_data_q: 2D array [32 chirps][512 range bins] of signed 16-bit Q
 
         Returns:
-            (doppler_map_i, doppler_map_q): 2D arrays [64 range bins][32 doppler bins]
+            (doppler_map_i, doppler_map_q): 2D arrays [512 range bins][32 doppler bins]
                                             of signed 16-bit
                                             Bins 0-15 = sub-frame 0 (long PRI)
                                             Bins 16-31 = sub-frame 1 (short PRI)
@@ -1216,7 +1222,7 @@ class SignalChain:
     IF_FREQ = 120_000_000    # IF frequency
     FTW_120MHZ = 0x4CCCCCCD  # Phase increment for 120 MHz at 400 MSPS
 
-    def __init__(self, twiddle_file_1024=None, twiddle_file_16=None):
+    def __init__(self, twiddle_file_2048=None, twiddle_file_16=None):
         self.nco = NCO()
         self.mixer = Mixer()
         self.cic_i = CICDecimator()
@@ -1224,7 +1230,7 @@ class SignalChain:
         self.fir_i = FIRFilter()
         self.fir_q = FIRFilter()
         self.ddc_interface = DDCInputInterface()
-        self.matched_filter = MatchedFilterChain(fft_size=1024, twiddle_file=twiddle_file_1024)
+        self.matched_filter = MatchedFilterChain(fft_size=2048, twiddle_file=twiddle_file_2048)
         self.range_decimator = RangeBinDecimator()
         self.doppler = DopplerProcessor(twiddle_file_16=twiddle_file_16)
 

9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py

@@ -2,34 +2,22 @@
 """
 gen_chirp_mem.py — Generate all chirp .mem files for AERIS-10 FPGA.
 
-Generates the 10 chirp .mem files used by chirp_memory_loader_param.v:
-  - long_chirp_seg{0,1,2,3}_{i,q}.mem  (8 files, 1024 lines each)
-  - short_chirp_{i,q}.mem              (2 files, 50 lines each)
+Generates the 6 chirp .mem files used by chirp_memory_loader_param.v:
+  - long_chirp_seg{0,1}_{i,q}.mem  (4 files, 2048 lines each)
+  - short_chirp_{i,q}.mem          (2 files, 50 lines each)
 
 Long chirp:
   The 3000-sample baseband chirp (30 us at 100 MHz system clock) is
-  segmented into 4 blocks of 1024 samples.  Each segment covers a
+  segmented into 2 blocks of 2048 samples.  Each segment covers a
   different time window of the chirp:
-    seg0: samples   0 .. 1023
-    seg1: samples 1024 .. 2047
-    seg2: samples 2048 .. 3071  (only 952 valid chirp samples; 72 zeros)
-    seg3: all zeros (seg3 starts at sample 3072, past chirp end at 3000)
+    seg0: samples    0 .. 2047
+    seg1: samples 2048 .. 4095  (only 952 valid chirp samples; 1096 zeros)
 
-  Wait — actually the memory loader stores 4*1024 = 4096 contiguous
-  samples indexed by {segment_select[1:0], sample_addr[9:0]}.  The
-  long chirp has 3000 samples, so:
-    seg0: chirp[0..1023]
-    seg1: chirp[1024..2047]
-    seg2: chirp[2048..2999] + 24 zeros  (samples 2048..3071 but chirp
-          ends at 2999, so indices 3000..3071 relative to full chirp
-          => mem indices 952..1023 in seg2 file are zero)
-
-  Wait, let me re-count.  seg2 covers global indices 2048..3071.
-  The chirp has samples 0..2999 (3000 samples).  So seg2 has valid
-  data at global indices 2048..2999 = 952 valid samples (seg2 file
-  indices 0..951), then zeros at file indices 952..1023 (72 zeros).
-
-  seg3 covers global indices 3072..4095, all past chirp end => all zeros.
+  The memory loader stores 2*2048 = 4096 contiguous samples indexed
+  by {segment_select[0], sample_addr[10:0]}.  The long chirp has
+  3000 samples, so:
+    seg0: chirp[0..2047] — all valid data
+    seg1: chirp[2048..2999] + 1096 zeros (samples past chirp end)
 
 Short chirp:
   50 samples (0.5 us at 100 MHz), same chirp formula with
@@ -47,22 +35,91 @@ Usage:
 
 import math
 import os
+import re
 import sys
 
 # ============================================================================
-# AERIS-10 Parameters (matching radar_scene.py)
+# AERIS-10 Parameters
+#
+# Sample counts / FFT size / segmentation come from radar_params.vh so a
+# change there (e.g. a new long-chirp duration) flows into the .mem files
+# automatically — no risk of Python and RTL disagreeing on buffer sizes.
+#
+# Physical chirp design constants (bandwidth, sample rate, Q15 scaling)
+# stay hardcoded here: they live outside radar_params.vh because they are
+# baseband-generation properties, not FPGA sizing parameters.
 # ============================================================================
+
+RADAR_PARAMS_VH = os.path.join(
+    os.path.dirname(os.path.abspath(__file__)), '..', '..', 'radar_params.vh'
+)
+
+
+def _parse_radar_params(path):
+    """
+    Parse `\\`define RP_<NAME>  <integer>` lines from radar_params.vh.
+    Only integer literals are supported (decimal / hex / binary); the
+    macros this script consumes are all integers. Comments / strings /
+    concat macros are ignored by the regex.
+    """
+    # Grab RHS up to an optional `// ...` comment, then parse as int.
+    line_pat = re.compile(r"^\s*`define\s+(RP_\w+)\s+([^/\n]+?)(?://.*)?$")
+    params = {}
+    with open(path) as f:
+        for line in f:
+            m = line_pat.match(line)
+            if not m:
+                continue
+            name, rhs = m.group(1), m.group(2).strip()
+            # Strip Verilog sized-literal prefix like 11'd2048 or 2'b00.
+            sized = re.match(r"\d+'([bdh])([0-9a-fA-F_]+)", rhs)
+            if sized:
+                base = {'b': 2, 'd': 10, 'h': 16}[sized.group(1)]
+                try:
+                    params[name] = int(sized.group(2).replace('_', ''), base)
+                except ValueError:
+                    continue
+                continue
+            # Plain integer (decimal or 0x...).
+            try:
+                params[name] = int(rhs, 0)
+            except ValueError:
+                # Non-integer macro (string, expression, cross-reference) —
+                # skip; this script only needs the integer sizing macros.
+                continue
+    return params
+
+
+_RP = _parse_radar_params(RADAR_PARAMS_VH)
+
+
+def _require(name):
+    if name not in _RP:
+        sys.stderr.write(
+            f"gen_chirp_mem.py: `{name}` not found in radar_params.vh; "
+            f"update the RTL macro or the parser.\n"
+        )
+        sys.exit(2)
+    return _RP[name]
+
+
+# Physical chirp design constants (not in radar_params.vh — baseband only).
 CHIRP_BW = 20e6           # 20 MHz sweep bandwidth
 FS_SYS = 100e6            # System clock (100 MHz, post-CIC)
-T_LONG_CHIRP = 30e-6      # 30 us long chirp duration
-T_SHORT_CHIRP = 0.5e-6    # 0.5 us short chirp duration
-FFT_SIZE = 1024
-LONG_CHIRP_SAMPLES = int(T_LONG_CHIRP * FS_SYS)   # 3000
-SHORT_CHIRP_SAMPLES = int(T_SHORT_CHIRP * FS_SYS)  # 50
-LONG_SEGMENTS = 4
 SCALE = 0.9               # Q15 scaling factor (matches radar_scene.py)
 Q15_MAX = 32767
 
+# Sizing / sample counts sourced from radar_params.vh (single source of truth).
+FFT_SIZE            = _require('RP_FFT_SIZE')
+LONG_CHIRP_SAMPLES  = _require('RP_LONG_CHIRP_SAMPLES_3KM')
+SHORT_CHIRP_SAMPLES = _require('RP_SHORT_CHIRP_SAMPLES')
+LONG_SEGMENTS       = _require('RP_LONG_SEGMENTS_3KM')
+
+# Durations are derived from sample counts + FS_SYS so a change to
+# RP_LONG_CHIRP_SAMPLES_3KM automatically re-targets the chirp rate.
+T_LONG_CHIRP  = LONG_CHIRP_SAMPLES  / FS_SYS
+T_SHORT_CHIRP = SHORT_CHIRP_SAMPLES / FS_SYS
+
 # Output directory (FPGA RTL root, where .mem files live)
 MEM_DIR = os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', '..')
 
@@ -187,13 +244,14 @@ def main():
     # Check magnitude envelope
     max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q, strict=False))
 
-    # Check seg3 zero padding
-    seg3_i_path = os.path.join(MEM_DIR, 'long_chirp_seg3_i.mem')
-    with open(seg3_i_path) as f:
-        seg3_lines = [line.strip() for line in f if line.strip()]
-    nonzero_seg3 = sum(1 for line in seg3_lines if line != '0000')
+    # Check seg1 zero padding (samples 3000-4095 should be zero)
+    seg1_i_path = os.path.join(MEM_DIR, 'long_chirp_seg1_i.mem')
+    with open(seg1_i_path) as f:
+        seg1_lines = [line.strip() for line in f if line.strip()]
+    # Indices 952..2047 in seg1 (global 3000..4095) should be zero
+    nonzero_tail = sum(1 for line in seg1_lines[952:] if line != '0000')
 
-    if nonzero_seg3 == 0:
+    if nonzero_tail == 0:
         pass
     else:
         pass

9_Firmware/9_2_FPGA/tb/cosim/gen_doppler_golden.py

@@ -35,9 +35,9 @@ from radar_scene import Target, generate_doppler_frame
 
 DOPPLER_FFT_SIZE = 16     # Per sub-frame
 DOPPLER_TOTAL_BINS = 32   # Total output (2 sub-frames x 16)
-RANGE_BINS = 64
+RANGE_BINS = 512
 CHIRPS_PER_FRAME = 32
-TOTAL_SAMPLES = CHIRPS_PER_FRAME * RANGE_BINS  # 2048
+TOTAL_SAMPLES = CHIRPS_PER_FRAME * RANGE_BINS  # 16384
 
 
 # =============================================================================

9_Firmware/9_2_FPGA/tb/cosim/gen_mf_cosim_golden.py

@@ -30,7 +30,7 @@ from fpga_model import (
 )
 
 
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 
 
 def load_hex_16bit(filepath):
@@ -143,9 +143,13 @@ def main():
         bb_q = load_hex_16bit(bb_q_path)
         ref_i = load_hex_16bit(ref_i_path)
         ref_q = load_hex_16bit(ref_q_path)
+        # Zero-pad to FFT_SIZE if shorter (legacy 1024-entry files → 2048)
+        for lst in [bb_i, bb_q, ref_i, ref_q]:
+            while len(lst) < FFT_SIZE:
+                lst.append(0)
         r = generate_case("chirp", bb_i, bb_q, ref_i, ref_q,
                           "Radar chirp: 2 targets (500m, 1500m) vs ref chirp",
-                          base_dir)
+                          base_dir, write_inputs=True)
         results.append(r)
     else:
         pass

9_Firmware/9_2_FPGA/tb/cosim/radar_scene.py

@@ -52,9 +52,11 @@ T_PRI_SHORT = 175e-6      # staggered short-PRI sub-frame
 N_SAMPLES_LISTEN = int(T_LISTEN_LONG * FS_ADC)  # 54800 samples
 
 # Processing chain
+# Updated for 2048-pt range FFT + 4x decimation → 512 range bins per chirp.
+# Must stay in sync with radar_params.vh: RP_FFT_SIZE=2048, RP_NUM_RANGE_BINS=512.
 CIC_DECIMATION = 4
-FFT_SIZE = 1024
-RANGE_BINS = 64
+FFT_SIZE = 2048
+RANGE_BINS = 512
 DOPPLER_FFT_SIZE = 16      # Per sub-frame
 DOPPLER_TOTAL_BINS = 32    # Total output bins (2 sub-frames x 16)
 CHIRPS_PER_SUBFRAME = 16

9_Firmware/9_2_FPGA/tb/gen_mf_golden_ref.py

@@ -22,7 +22,7 @@ Usage:
 import os
 import numpy as np
 
-N = 1024  # FFT length
+N = 2048  # FFT length — matches `RP_FFT_SIZE` (radar_params.vh)
 
 
 def to_q15(value):